From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 5357A3E22910; Mon, 19 Dec 2022 09:40:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5357A3E22910 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1671442834; bh=PPVr0+AveHC8tHLZn+fkL+1cLxgsEGqmPdxlIA/tFVE=; h=From:To:Subject:Date:From; b=n8NIGbidCjzOjogEBYKJIhmfISyQo14JsP6oYAfeyoh6a8/w2TFXA7LynPVHjR+4f EdW68Q7zpiHImr0JuuWsTTKT0kylixMigHzvbAy9E7bqSV96f2YNL4zvrnCrJQzr9V s8dMWju1euYZNkkVoOT6pFJcBjTHY7nCNyrNKZEk= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4772] RISC-V: Fix vwrite_csr.c and vread_csr.c X-Act-Checkin: gcc X-Git-Author: Kito Cheng X-Git-Refname: refs/heads/master X-Git-Oldrev: 97a8e88cd7d22562c0ea4f73687d3c93c21e12fb X-Git-Newrev: b346e77f4d7b482df78f119819b1e06a544ef515 Message-Id: <20221219094034.5357A3E22910@sourceware.org> Date: Mon, 19 Dec 2022 09:40:34 +0000 (GMT) List-Id: https://gcc.gnu.org/g:b346e77f4d7b482df78f119819b1e06a544ef515 commit r13-4772-gb346e77f4d7b482df78f119819b1e06a544ef515 Author: Kito Cheng Date: Mon Dec 19 17:28:25 2022 +0800 RISC-V: Fix vwrite_csr.c and vread_csr.c gcc/testsuite: * gcc.target/riscv/rvv/base/vread_csr.c: Use specific option instead. * gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto. Diff: --- gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c | 3 +-- gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c index 69c9c1fa5ca..ac5484fb023 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O3" } */ -/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c index f9b4e8848df..830ddb95d16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O3" } */ -/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ #include "riscv_vector.h"