From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 1BE503858D1E; Mon, 19 Dec 2022 14:24:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1BE503858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1671459842; bh=3n5WBjOD7OWR+RU3gzYx3QKF+gqzuRJfbHQMzRo2a4U=; h=From:To:Subject:Date:From; b=Mo5wEF/Kmo3cGJik8k9GQBrJFQuVgSBOlh6kZb9evBKXmqIEsojWeGKK+ZAthAo5D Mf2ZNm3x0CWeFrHw6PZI0vaNbMrgrnEfvVScM7XDEP4vihX0kXGxl/V9G9koUvW38e D03nC0sdOe2UHN8D7rWbrv82R5+hrqKd6CiiG2FQ= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4784] RISC-V: Fix RVV machine mode attribute configuration X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 6e85f89a7d59a99a3395b6e153b99262a58b2f6c X-Git-Newrev: 22dc669e109de9a76c74535cdf30e7922e0ef5c1 Message-Id: <20221219142402.1BE503858D1E@sourceware.org> Date: Mon, 19 Dec 2022 14:24:02 +0000 (GMT) List-Id: https://gcc.gnu.org/g:22dc669e109de9a76c74535cdf30e7922e0ef5c1 commit r13-4784-g22dc669e109de9a76c74535cdf30e7922e0ef5c1 Author: Ju-Zhe Zhong Date: Wed Dec 14 15:01:56 2022 +0800 RISC-V: Fix RVV machine mode attribute configuration The attribute configuration of each machine mode are support in the previous patch. I noticed some of them are not correct during VSETVL PASS testsing. Correct them in the single patch now. gcc/ChangeLog: * config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes. Diff: --- gcc/config/riscv/riscv-vector-switch.def | 38 ++++++++++++++++---------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index a51f45be487..ec12be84661 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -95,16 +95,16 @@ TODO: FP16 vector needs support of 'zvfh', we don't support it yet. */ #endif /* Mask modes. Disable VNx64BImode when TARGET_MIN_VLEN == 32. */ -ENTRY (VNx64BI, TARGET_MIN_VLEN > 32, LMUL_F8, 64, LMUL_RESERVED, 0) -ENTRY (VNx32BI, true, LMUL_F4, 32, LMUL_RESERVED, 0) -ENTRY (VNx16BI, true, LMUL_F2, 16, LMUL_RESERVED, 0) -ENTRY (VNx8BI, true, LMUL_1, 8, LMUL_RESERVED, 0) -ENTRY (VNx4BI, true, LMUL_2, 4, LMUL_RESERVED, 0) -ENTRY (VNx2BI, true, LMUL_4, 2, LMUL_RESERVED, 0) -ENTRY (VNx1BI, true, LMUL_8, 1, LMUL_RESERVED, 0) +ENTRY (VNx64BI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 1) +ENTRY (VNx32BI, true, LMUL_8, 1, LMUL_4, 2) +ENTRY (VNx16BI, true, LMUL_4, 2, LMUL_2, 4) +ENTRY (VNx8BI, true, LMUL_2, 4, LMUL_1, 8) +ENTRY (VNx4BI, true, LMUL_1, 8, LMUL_F2, 16) +ENTRY (VNx2BI, true, LMUL_F2, 16, LMUL_F4, 32) +ENTRY (VNx1BI, true, LMUL_F4, 32, LMUL_F8, 64) /* SEW = 8. Disable VNx64QImode when TARGET_MIN_VLEN == 32. */ -ENTRY (VNx64QI, TARGET_MIN_VLEN > 32, LMUL_8, 1, LMUL_RESERVED, 0) +ENTRY (VNx64QI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 1) ENTRY (VNx32QI, true, LMUL_8, 1, LMUL_4, 2) ENTRY (VNx16QI, true, LMUL_4, 2, LMUL_2, 4) ENTRY (VNx8QI, true, LMUL_2, 4, LMUL_1, 8) @@ -113,7 +113,7 @@ ENTRY (VNx2QI, true, LMUL_F2, 16, LMUL_F4, 32) ENTRY (VNx1QI, true, LMUL_F4, 32, LMUL_F8, 64) /* SEW = 16. Disable VNx32HImode when TARGET_MIN_VLEN == 32. */ -ENTRY (VNx32HI, TARGET_MIN_VLEN > 32, LMUL_8, 2, LMUL_RESERVED, 0) +ENTRY (VNx32HI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 2) ENTRY (VNx16HI, true, LMUL_8, 2, LMUL_4, 4) ENTRY (VNx8HI, true, LMUL_4, 4, LMUL_2, 8) ENTRY (VNx4HI, true, LMUL_2, 8, LMUL_1, 16) @@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32) ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64) /* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported. */ -ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0) +ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2) ENTRY (VNx16HF, false, LMUL_8, 2, LMUL_4, 4) ENTRY (VNx8HF, false, LMUL_4, 4, LMUL_2, 8) ENTRY (VNx4HF, false, LMUL_2, 8, LMUL_1, 16) @@ -131,18 +131,18 @@ ENTRY (VNx1HF, false, LMUL_F2, 32, LMUL_F4, 64) /* SEW = 32. Disable VNx16SImode when TARGET_MIN_VLEN == 32. For single-precision floating-point, we need TARGET_VECTOR_FP32 == RVV_ENABLE. */ -ENTRY (VNx16SI, TARGET_MIN_VLEN > 32, LMUL_8, 4, LMUL_RESERVED, 0) +ENTRY (VNx16SI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 4) ENTRY (VNx8SI, true, LMUL_8, 4, LMUL_4, 8) -ENTRY (VNx4SI, true, LMUL_4, 8, LMUL_2, 4) -ENTRY (VNx2SI, true, LMUL_2, 16, LMUL_1, 2) -ENTRY (VNx1SI, true, LMUL_1, 32, LMUL_F2, 1) +ENTRY (VNx4SI, true, LMUL_4, 8, LMUL_2, 16) +ENTRY (VNx2SI, true, LMUL_2, 16, LMUL_1, 32) +ENTRY (VNx1SI, true, LMUL_1, 32, LMUL_F2, 64) -ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32), LMUL_8, 4, - LMUL_RESERVED, 0) +ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32), LMUL_RESERVED, 0, + LMUL_8, 4) ENTRY (VNx8SF, TARGET_VECTOR_FP32, LMUL_8, 4, LMUL_4, 8) -ENTRY (VNx4SF, TARGET_VECTOR_FP32, LMUL_4, 8, LMUL_2, 4) -ENTRY (VNx2SF, TARGET_VECTOR_FP32, LMUL_2, 16, LMUL_1, 2) -ENTRY (VNx1SF, TARGET_VECTOR_FP32, LMUL_1, 32, LMUL_F2, 1) +ENTRY (VNx4SF, TARGET_VECTOR_FP32, LMUL_4, 8, LMUL_2, 16) +ENTRY (VNx2SF, TARGET_VECTOR_FP32, LMUL_2, 16, LMUL_1, 32) +ENTRY (VNx1SF, TARGET_VECTOR_FP32, LMUL_1, 32, LMUL_F2, 64) /* SEW = 64. Enable when TARGET_MIN_VLEN > 32. For double-precision floating-point, we need TARGET_VECTOR_FP64 ==