From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 965333858C36; Mon, 19 Dec 2022 14:24:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 965333858C36 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1671459862; bh=SnCL32fPFhcPTDk4sEkw150ltC+KPSkGUAhUfnhdBic=; h=From:To:Subject:Date:From; b=F2DAbUjmuTpKKf3IvBtC6aW+m7I1f738PdB5qHxURF7cjmEmQiVyyUEAvdXkBxQI2 MniX838niGwdLByGf41KgO6Ou+sfxAd3RNZr5mIRIAFPOIM+Gas2IKGEwS1Qg/Gn8w dX6QoCbjtUVYWeQvWZ+eoJo+R9pw05PXcJVo8jmo= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4788] RISC-V: Add testcases for VSETVL PASS 2 X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: e4433e075fc4ef06401c2255561ee6a508a49dcb X-Git-Newrev: 6f18836ca035d3d029cdc503e2a0d7d685a4d072 Message-Id: <20221219142422.965333858C36@sourceware.org> Date: Mon, 19 Dec 2022 14:24:22 +0000 (GMT) List-Id: https://gcc.gnu.org/g:6f18836ca035d3d029cdc503e2a0d7d685a4d072 commit r13-4788-g6f18836ca035d3d029cdc503e2a0d7d685a4d072 Author: Ju-Zhe Zhong Date: Wed Dec 14 16:13:01 2022 +0800 RISC-V: Add testcases for VSETVL PASS 2 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: New test. Diff: --- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c | 217 +++++++++++++++++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c | 40 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c | 237 +++++++++++++++++++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c | 37 ++++ .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c | 37 ++++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-1.c | 26 +++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 47 ++++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 55 +++++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 55 +++++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-13.c | 17 ++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c | 39 ++++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c | 52 +++++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c | 60 ++++++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-2.c | 26 +++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-3.c | 25 +++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 20 ++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 20 ++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 33 +++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 43 ++++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 45 ++++ .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 45 ++++ 44 files changed, 2063 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c new file mode 100644 index 00000000000..cd58e53a822 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint8mf8_t v = *(vint8mf8_t*)(in + 100); + *(vint8mf8_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint8mf8_t v = *(vint8mf8_t*)(in + 200); + *(vint8mf8_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint8mf8_t v = *(vint8mf8_t*)(in + 300); + *(vint8mf8_t*)(out + 300) = v; + } + else + { + vint8mf8_t v = *(vint8mf8_t*)(in + 400); + *(vint8mf8_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vint8mf8_t v = *(vint8mf8_t*)(in + i); + *(vint8mf8_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,\.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c new file mode 100644 index 00000000000..1aaebdf4bc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + 100); + *(vuint16mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + 200); + *(vuint16mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + 300); + *(vuint16mf2_t*)(out + 300) = v; + } + else + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + 400); + *(vuint16mf2_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + i); + *(vuint16mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c new file mode 100644 index 00000000000..813ea49e705 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint32mf2_t v = *(vint32mf2_t*)(in + 100); + *(vint32mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint32mf2_t v = *(vint32mf2_t*)(in + 200); + *(vint32mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint32mf2_t v = *(vint32mf2_t*)(in + 300); + *(vint32mf2_t*)(out + 300) = v; + } + else + { + vint32mf2_t v = *(vint32mf2_t*)(in + 400); + *(vint32mf2_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vint32mf2_t v = *(vint32mf2_t*)(in + i); + *(vint32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c new file mode 100644 index 00000000000..9b59df9f78b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + 100); + *(vuint32mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + 200); + *(vuint32mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + 300); + *(vuint32mf2_t*)(out + 300) = v; + } + else + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + 400); + *(vuint32mf2_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + i); + *(vuint32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c new file mode 100644 index 00000000000..35e4fd190af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100); + *(vfloat32mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200); + *(vfloat32mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300); + *(vfloat32mf2_t*)(out + 300) = v; + } + else + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400); + *(vfloat32mf2_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i); + *(vfloat32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c new file mode 100644 index 00000000000..2330d34246f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c @@ -0,0 +1,217 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool64_t v = *(vbool64_t*)(in + 100); + *(vbool64_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool64_t v = *(vbool64_t*)(in + 200); + *(vbool64_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool64_t v = *(vbool64_t*)(in + 300); + *(vbool64_t*)(out + 300) = v; + } + else + { + vbool64_t v = *(vbool64_t*)(in + 400); + *(vbool64_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vbool64_t v = *(vbool64_t*)(in + i); + *(vbool64_t*)(out + i) = v; + } +} + +void f2 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool32_t v = *(vbool32_t*)(in + 100); + *(vbool32_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool32_t v = *(vbool32_t*)(in + 200); + *(vbool32_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool32_t v = *(vbool32_t*)(in + 300); + *(vbool32_t*)(out + 300) = v; + } + else + { + vbool32_t v = *(vbool32_t*)(in + 400); + *(vbool32_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vbool32_t v = *(vbool32_t*)(in + i); + *(vbool32_t*)(out + i) = v; + } +} + +void f3 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool16_t v = *(vbool16_t*)(in + 100); + *(vbool16_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool16_t v = *(vbool16_t*)(in + 200); + *(vbool16_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool16_t v = *(vbool16_t*)(in + 300); + *(vbool16_t*)(out + 300) = v; + } + else + { + vbool16_t v = *(vbool16_t*)(in + 400); + *(vbool16_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vbool16_t v = *(vbool16_t*)(in + i); + *(vbool16_t*)(out + i) = v; + } +} + +void f4 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool8_t v = *(vbool8_t*)(in + 100); + *(vbool8_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool8_t v = *(vbool8_t*)(in + 200); + *(vbool8_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool8_t v = *(vbool8_t*)(in + 300); + *(vbool8_t*)(out + 300) = v; + } + else + { + vbool8_t v = *(vbool8_t*)(in + 400); + *(vbool8_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vbool8_t v = *(vbool8_t*)(in + i); + *(vbool8_t*)(out + i) = v; + } +} + +void f5 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool4_t v = *(vbool4_t*)(in + 100); + *(vbool4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool4_t v = *(vbool4_t*)(in + 200); + *(vbool4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool4_t v = *(vbool4_t*)(in + 300); + *(vbool4_t*)(out + 300) = v; + } + else + { + vbool4_t v = *(vbool4_t*)(in + 400); + *(vbool4_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vbool4_t v = *(vbool4_t*)(in + i); + *(vbool4_t*)(out + i) = v; + } +} + +void f6 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool2_t v = *(vbool2_t*)(in + 100); + *(vbool2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool2_t v = *(vbool2_t*)(in + 200); + *(vbool2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool2_t v = *(vbool2_t*)(in + 300); + *(vbool2_t*)(out + 300) = v; + } + else + { + vbool2_t v = *(vbool2_t*)(in + 400); + *(vbool2_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vbool2_t v = *(vbool2_t*)(in + i); + *(vbool2_t*)(out + i) = v; + } +} + +void f7 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool1_t v = *(vbool1_t*)(in + 100); + *(vbool1_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool1_t v = *(vbool1_t*)(in + 200); + *(vbool1_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool1_t v = *(vbool1_t*)(in + 300); + *(vbool1_t*)(out + 300) = v; + } + else + { + vbool1_t v = *(vbool1_t*)(in + 400); + *(vbool1_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vbool1_t v = *(vbool1_t*)(in + i); + *(vbool1_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c new file mode 100644 index 00000000000..687ecdf0fa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint8mf8_t v = *(vint8mf8_t*)(in + 100); + *(vint8mf8_t*)(out + 100) = v; + break; + } + case 2:{ + vint8mf8_t v = *(vint8mf8_t*)(in + 200); + *(vint8mf8_t*)(out + 100) = v; + break; + } + case 3:{ + vint8mf8_t v = *(vint8mf8_t*)(in + 300); + *(vint8mf8_t*)(out + 100) = v; + break; + } + default:{ + vint8mf8_t v = *(vint8mf8_t*)(in + 400); + *(vint8mf8_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vint8mf8_t v = *(vint8mf8_t*)(in + i); + *(vint8mf8_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c new file mode 100644 index 00000000000..d644fb69955 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint8mf8_t v = *(vuint8mf8_t*)(in + 100); + *(vuint8mf8_t*)(out + 100) = v; + break; + } + case 2:{ + vuint8mf8_t v = *(vuint8mf8_t*)(in + 200); + *(vuint8mf8_t*)(out + 100) = v; + break; + } + case 3:{ + vuint8mf8_t v = *(vuint8mf8_t*)(in + 300); + *(vuint8mf8_t*)(out + 100) = v; + break; + } + default:{ + vuint8mf8_t v = *(vuint8mf8_t*)(in + 400); + *(vuint8mf8_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + i); + *(vuint8mf8_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c new file mode 100644 index 00000000000..ea4d95554bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint8mf4_t v = *(vint8mf4_t*)(in + 100); + *(vint8mf4_t*)(out + 100) = v; + break; + } + case 2:{ + vint8mf4_t v = *(vint8mf4_t*)(in + 200); + *(vint8mf4_t*)(out + 100) = v; + break; + } + case 3:{ + vint8mf4_t v = *(vint8mf4_t*)(in + 300); + *(vint8mf4_t*)(out + 100) = v; + break; + } + default:{ + vint8mf4_t v = *(vint8mf4_t*)(in + 400); + *(vint8mf4_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vint8mf4_t v = *(vint8mf4_t*)(in + i); + *(vint8mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c new file mode 100644 index 00000000000..cbbffb78966 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint8mf4_t v = *(vuint8mf4_t*)(in + 100); + *(vuint8mf4_t*)(out + 100) = v; + break; + } + case 2:{ + vuint8mf4_t v = *(vuint8mf4_t*)(in + 200); + *(vuint8mf4_t*)(out + 100) = v; + break; + } + case 3:{ + vuint8mf4_t v = *(vuint8mf4_t*)(in + 300); + *(vuint8mf4_t*)(out + 100) = v; + break; + } + default:{ + vuint8mf4_t v = *(vuint8mf4_t*)(in + 400); + *(vuint8mf4_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + i); + *(vuint8mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c new file mode 100644 index 00000000000..21d5cc91310 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint8mf2_t v = *(vint8mf2_t*)(in + 100); + *(vint8mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vint8mf2_t v = *(vint8mf2_t*)(in + 200); + *(vint8mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vint8mf2_t v = *(vint8mf2_t*)(in + 300); + *(vint8mf2_t*)(out + 100) = v; + break; + } + default:{ + vint8mf2_t v = *(vint8mf2_t*)(in + 400); + *(vint8mf2_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vint8mf2_t v = *(vint8mf2_t*)(in + i); + *(vint8mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c new file mode 100644 index 00000000000..39d523b6676 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + 100); + *(vuint8mf8_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + 200); + *(vuint8mf8_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + 300); + *(vuint8mf8_t*)(out + 300) = v; + } + else + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + 400); + *(vuint8mf8_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + i); + *(vuint8mf8_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c new file mode 100644 index 00000000000..29dd2d6a774 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint8mf2_t v = *(vuint8mf2_t*)(in + 100); + *(vuint8mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vuint8mf2_t v = *(vuint8mf2_t*)(in + 200); + *(vuint8mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vuint8mf2_t v = *(vuint8mf2_t*)(in + 300); + *(vuint8mf2_t*)(out + 100) = v; + break; + } + default:{ + vuint8mf2_t v = *(vuint8mf2_t*)(in + 400); + *(vuint8mf2_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + i); + *(vuint8mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c new file mode 100644 index 00000000000..286a7439fb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint16mf4_t v = *(vint16mf4_t*)(in + 100); + *(vint16mf4_t*)(out + 100) = v; + break; + } + case 2:{ + vint16mf4_t v = *(vint16mf4_t*)(in + 200); + *(vint16mf4_t*)(out + 100) = v; + break; + } + case 3:{ + vint16mf4_t v = *(vint16mf4_t*)(in + 300); + *(vint16mf4_t*)(out + 100) = v; + break; + } + default:{ + vint16mf4_t v = *(vint16mf4_t*)(in + 400); + *(vint16mf4_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vint16mf4_t v = *(vint16mf4_t*)(in + i); + *(vint16mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c new file mode 100644 index 00000000000..4cd8a5dfc79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint16mf4_t v = *(vuint16mf4_t*)(in + 100); + *(vuint16mf4_t*)(out + 100) = v; + break; + } + case 2:{ + vuint16mf4_t v = *(vuint16mf4_t*)(in + 200); + *(vuint16mf4_t*)(out + 100) = v; + break; + } + case 3:{ + vuint16mf4_t v = *(vuint16mf4_t*)(in + 300); + *(vuint16mf4_t*)(out + 100) = v; + break; + } + default:{ + vuint16mf4_t v = *(vuint16mf4_t*)(in + 400); + *(vuint16mf4_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + i); + *(vuint16mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c new file mode 100644 index 00000000000..5825f12a577 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint16mf2_t v = *(vint16mf2_t*)(in + 100); + *(vint16mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vint16mf2_t v = *(vint16mf2_t*)(in + 200); + *(vint16mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vint16mf2_t v = *(vint16mf2_t*)(in + 300); + *(vint16mf2_t*)(out + 100) = v; + break; + } + default:{ + vint16mf2_t v = *(vint16mf2_t*)(in + 400); + *(vint16mf2_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vint16mf2_t v = *(vint16mf2_t*)(in + i); + *(vint16mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c new file mode 100644 index 00000000000..e2b53313ee1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint16mf2_t v = *(vuint16mf2_t*)(in + 100); + *(vuint16mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vuint16mf2_t v = *(vuint16mf2_t*)(in + 200); + *(vuint16mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vuint16mf2_t v = *(vuint16mf2_t*)(in + 300); + *(vuint16mf2_t*)(out + 100) = v; + break; + } + default:{ + vuint16mf2_t v = *(vuint16mf2_t*)(in + 400); + *(vuint16mf2_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + i); + *(vuint16mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c new file mode 100644 index 00000000000..f40ff57f57f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint32mf2_t v = *(vint32mf2_t*)(in + 100); + *(vint32mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vint32mf2_t v = *(vint32mf2_t*)(in + 200); + *(vint32mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vint32mf2_t v = *(vint32mf2_t*)(in + 300); + *(vint32mf2_t*)(out + 100) = v; + break; + } + default:{ + vint32mf2_t v = *(vint32mf2_t*)(in + 400); + *(vint32mf2_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vint32mf2_t v = *(vint32mf2_t*)(in + i); + *(vint32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c new file mode 100644 index 00000000000..26a9933e8e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint32mf2_t v = *(vuint32mf2_t*)(in + 100); + *(vuint32mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vuint32mf2_t v = *(vuint32mf2_t*)(in + 200); + *(vuint32mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vuint32mf2_t v = *(vuint32mf2_t*)(in + 300); + *(vuint32mf2_t*)(out + 100) = v; + break; + } + default:{ + vuint32mf2_t v = *(vuint32mf2_t*)(in + 400); + *(vuint32mf2_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + i); + *(vuint32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c new file mode 100644 index 00000000000..7028d9118bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100); + *(vfloat32mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200); + *(vfloat32mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300); + *(vfloat32mf2_t*)(out + 100) = v; + break; + } + default:{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400); + *(vfloat32mf2_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i); + *(vfloat32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c new file mode 100644 index 00000000000..aa4c1a7f51d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c @@ -0,0 +1,237 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool64_t v = *(vbool64_t*)(in + 100); + *(vbool64_t*)(out + 100) = v; + break; + } + case 2:{ + vbool64_t v = *(vbool64_t*)(in + 200); + *(vbool64_t*)(out + 100) = v; + break; + } + case 3:{ + vbool64_t v = *(vbool64_t*)(in + 300); + *(vbool64_t*)(out + 100) = v; + break; + } + default:{ + vbool64_t v = *(vbool64_t*)(in + 400); + *(vbool64_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vbool64_t v = *(vbool64_t*)(in + i); + *(vbool64_t*)(out + i) = v; + } +} + +void f2 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool32_t v = *(vbool32_t*)(in + 100); + *(vbool32_t*)(out + 100) = v; + break; + } + case 2:{ + vbool32_t v = *(vbool32_t*)(in + 200); + *(vbool32_t*)(out + 100) = v; + break; + } + case 3:{ + vbool32_t v = *(vbool32_t*)(in + 300); + *(vbool32_t*)(out + 100) = v; + break; + } + default:{ + vbool32_t v = *(vbool32_t*)(in + 400); + *(vbool32_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vbool32_t v = *(vbool32_t*)(in + i); + *(vbool32_t*)(out + i) = v; + } +} + +void f3 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool16_t v = *(vbool16_t*)(in + 100); + *(vbool16_t*)(out + 100) = v; + break; + } + case 2:{ + vbool16_t v = *(vbool16_t*)(in + 200); + *(vbool16_t*)(out + 100) = v; + break; + } + case 3:{ + vbool16_t v = *(vbool16_t*)(in + 300); + *(vbool16_t*)(out + 100) = v; + break; + } + default:{ + vbool16_t v = *(vbool16_t*)(in + 400); + *(vbool16_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vbool16_t v = *(vbool16_t*)(in + i); + *(vbool16_t*)(out + i) = v; + } +} + +void f4 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool8_t v = *(vbool8_t*)(in + 100); + *(vbool8_t*)(out + 100) = v; + break; + } + case 2:{ + vbool8_t v = *(vbool8_t*)(in + 200); + *(vbool8_t*)(out + 100) = v; + break; + } + case 3:{ + vbool8_t v = *(vbool8_t*)(in + 300); + *(vbool8_t*)(out + 100) = v; + break; + } + default:{ + vbool8_t v = *(vbool8_t*)(in + 400); + *(vbool8_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vbool8_t v = *(vbool8_t*)(in + i); + *(vbool8_t*)(out + i) = v; + } +} + +void f5 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool4_t v = *(vbool4_t*)(in + 100); + *(vbool4_t*)(out + 100) = v; + break; + } + case 2:{ + vbool4_t v = *(vbool4_t*)(in + 200); + *(vbool4_t*)(out + 100) = v; + break; + } + case 3:{ + vbool4_t v = *(vbool4_t*)(in + 300); + *(vbool4_t*)(out + 100) = v; + break; + } + default:{ + vbool4_t v = *(vbool4_t*)(in + 400); + *(vbool4_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vbool4_t v = *(vbool4_t*)(in + i); + *(vbool4_t*)(out + i) = v; + } +} + +void f6 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool2_t v = *(vbool2_t*)(in + 100); + *(vbool2_t*)(out + 100) = v; + break; + } + case 2:{ + vbool2_t v = *(vbool2_t*)(in + 200); + *(vbool2_t*)(out + 100) = v; + break; + } + case 3:{ + vbool2_t v = *(vbool2_t*)(in + 300); + *(vbool2_t*)(out + 100) = v; + break; + } + default:{ + vbool2_t v = *(vbool2_t*)(in + 400); + *(vbool2_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vbool2_t v = *(vbool2_t*)(in + i); + *(vbool2_t*)(out + i) = v; + } +} + +void f7 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool1_t v = *(vbool1_t*)(in + 100); + *(vbool1_t*)(out + 100) = v; + break; + } + case 2:{ + vbool1_t v = *(vbool1_t*)(in + 200); + *(vbool1_t*)(out + 100) = v; + break; + } + case 3:{ + vbool1_t v = *(vbool1_t*)(in + 300); + *(vbool1_t*)(out + 100) = v; + break; + } + default:{ + vbool1_t v = *(vbool1_t*)(in + 400); + *(vbool1_t*)(out + 400) = v; + break; + } + } + for (int i = 0; i < n; i++) + { + vbool1_t v = *(vbool1_t*)(in + i); + *(vbool1_t*)(out + i) = v; + } +} +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vlm\.v\s*(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c new file mode 100644 index 00000000000..41585d012e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint8mf4_t v = *(vint8mf4_t*)(in + 100); + *(vint8mf4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint8mf4_t v = *(vint8mf4_t*)(in + 200); + *(vint8mf4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint8mf4_t v = *(vint8mf4_t*)(in + 300); + *(vint8mf4_t*)(out + 300) = v; + } + else + { + vint8mf4_t v = *(vint8mf4_t*)(in + 400); + *(vint8mf4_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vint8mf4_t v = *(vint8mf4_t*)(in + i); + *(vint8mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c new file mode 100644 index 00000000000..d4890e31ff0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + 100); + *(vuint8mf4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + 200); + *(vuint8mf4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + 300); + *(vuint8mf4_t*)(out + 300) = v; + } + else + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + 400); + *(vuint8mf4_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + i); + *(vuint8mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c new file mode 100644 index 00000000000..53905fca6fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint8mf2_t v = *(vint8mf2_t*)(in + 100); + *(vint8mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint8mf2_t v = *(vint8mf2_t*)(in + 200); + *(vint8mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint8mf2_t v = *(vint8mf2_t*)(in + 300); + *(vint8mf2_t*)(out + 300) = v; + } + else + { + vint8mf2_t v = *(vint8mf2_t*)(in + 400); + *(vint8mf2_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vint8mf2_t v = *(vint8mf2_t*)(in + i); + *(vint8mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c new file mode 100644 index 00000000000..4d56ec53540 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + 100); + *(vuint8mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + 200); + *(vuint8mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + 300); + *(vuint8mf2_t*)(out + 300) = v; + } + else + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + 400); + *(vuint8mf2_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + i); + *(vuint8mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c new file mode 100644 index 00000000000..f722ec49c02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint16mf4_t v = *(vint16mf4_t*)(in + 100); + *(vint16mf4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint16mf4_t v = *(vint16mf4_t*)(in + 200); + *(vint16mf4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint16mf4_t v = *(vint16mf4_t*)(in + 300); + *(vint16mf4_t*)(out + 300) = v; + } + else + { + vint16mf4_t v = *(vint16mf4_t*)(in + 400); + *(vint16mf4_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vint16mf4_t v = *(vint16mf4_t*)(in + i); + *(vint16mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c new file mode 100644 index 00000000000..69bd0be5fd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + 100); + *(vuint16mf4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + 200); + *(vuint16mf4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + 300); + *(vuint16mf4_t*)(out + 300) = v; + } + else + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + 400); + *(vuint16mf4_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + i); + *(vuint16mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c new file mode 100644 index 00000000000..208173fb4bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint16mf2_t v = *(vint16mf2_t*)(in + 100); + *(vint16mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint16mf2_t v = *(vint16mf2_t*)(in + 200); + *(vint16mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint16mf2_t v = *(vint16mf2_t*)(in + 300); + *(vint16mf2_t*)(out + 300) = v; + } + else + { + vint16mf2_t v = *(vint16mf2_t*)(in + 400); + *(vint16mf2_t*)(out + 400) = v; + } + for (int i = 0; i < n; i++) + { + vint16mf2_t v = *(vint16mf2_t*)(in + i); + *(vint16mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c new file mode 100644 index 00000000000..c8601a69281 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int n) +{ + vint8mf8_t v1 = *(vint8mf8_t*)(in + 1); + vint16mf4_t v2 = *(vint16mf4_t*)(in + 2); + vint32mf2_t v3 = *(vint32mf2_t*)(in + 3); + vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4); + + *(vint8mf8_t*)(out + 1) = v1; + *(vint16mf4_t*)(out + 2) = v2; + *(vint32mf2_t*)(out + 3) = v3; + *(vfloat32mf2_t*)(out + 4) = v4; + + for (int i = 0; i < n; i++) + { + vint8mf8_t v = *(vint8mf8_t*)(in + i + 5); + *(vint8mf8_t*)(out + i + 5) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c new file mode 100644 index 00000000000..b68932a6802 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond) +{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000); + *(vfloat32mf2_t*)(out + 10000) = v; + + if (cond) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 30000); + *(vfloat32mf2_t*)(out + 30000) = v; + } + else + { + vint16mf2_t v = *(vint16mf2_t*)(in + 20000); + *(vint16mf2_t*)(out + 20000) = v; + } + + for (int i = 0; i < n; i++) + { + vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100); + + vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200); + vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300); + vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400); + vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500); + vbool1_t v5 = *(vbool1_t*)(in + i + 600); + + vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700); + + *(vint32mf2_t*)(out + i + 100) = v0; + *(vint16mf2_t*)(out + i + 200) = v1; + *(vint8mf2_t*)(out + i + 300) = v2; + *(vint8mf4_t*)(out + i + 400) = v3; + *(vint8mf8_t*)(out + i + 500) = v4; + *(vbool1_t*)(out + i + 600) = v5; + *(vint32mf2_t*)(out + i + 700) = v6; + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {\s*\.L[0-9]+:\s*vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c new file mode 100644 index 00000000000..a6530a2712f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond1, int cond2) +{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000); + *(vfloat32mf2_t*)(out + 10000) = v; + + if (cond1) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 30000); + *(vfloat32mf2_t*)(out + 30000) = v; + } + else + { + vint8mf8_t v = *(vint8mf8_t*)(in + 20000); + *(vint8mf8_t*)(out + 20000) = v; + } + + for (int i = 0; i < n; i++) + { + vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100); + + vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200); + vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300); + vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400); + vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500); + vbool1_t v5 = *(vbool1_t*)(in + i + 600); + + vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700); + + *(vint32mf2_t*)(out + i + 100) = v0; + *(vint16mf2_t*)(out + i + 200) = v1; + *(vint8mf2_t*)(out + i + 300) = v2; + *(vint8mf4_t*)(out + i + 400) = v3; + *(vint8mf8_t*)(out + i + 500) = v4; + *(vbool1_t*)(out + i + 600) = v5; + *(vint32mf2_t*)(out + i + 700) = v6; + } + + if (cond2) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 40000); + *(vfloat32mf2_t*)(out + 40000) = v; + } + else + { + vint16mf4_t v = *(vint16mf4_t*)(in + 30000); + *(vint16mf4_t*)(out + 30000) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c new file mode 100644 index 00000000000..eaf69928d44 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond1, int cond2) +{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000); + *(vfloat32mf2_t*)(out + 10000) = v; + + if (cond1) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 30000); + *(vfloat32mf2_t*)(out + 30000) = v; + } + else + { + vint8mf2_t v = *(vint8mf2_t*)(in + 20000); + *(vint8mf2_t*)(out + 20000) = v; + } + + for (int i = 0; i < n; i++) + { + vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100); + + vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200); + vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300); + vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400); + vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500); + vbool1_t v5 = *(vbool1_t*)(in + i + 600); + + vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700); + + *(vint32mf2_t*)(out + i + 100) = v0; + *(vint16mf2_t*)(out + i + 200) = v1; + *(vint8mf2_t*)(out + i + 300) = v2; + *(vint8mf4_t*)(out + i + 400) = v3; + *(vint8mf8_t*)(out + i + 500) = v4; + *(vbool1_t*)(out + i + 600) = v5; + *(vint32mf2_t*)(out + i + 700) = v6; + } + + if (cond2) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 40000); + *(vfloat32mf2_t*)(out + 40000) = v; + } + else + { + vint16mf4_t v = *(vint16mf4_t*)(in + 30000); + *(vint16mf4_t*)(out + 30000) = v; + } +} +/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c new file mode 100644 index 00000000000..1f6ed17437a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int n) +{ + vint8mf8_t v1; + vint16mf4_t v2; + + *(vint8mf8_t*)(out + 1) = v1; + *(vint16mf4_t*)(out + 2) = v2; +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c new file mode 100644 index 00000000000..291916f2600 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond) +{ + for (int i = 0; i < n; i++) { + vint16mf4_t v; + *(vint16mf4_t*)(out + i + 700) = v; + } + for (int i = 0; i < n; i++) { + a[i] = a[i] + b[i]; + } + for (int i = 0; i < n; i++) { + a[i] = a[i] * b[i]; + } + for (int i = 0; i < n; i++) { + a[i] = a[i] - b[i]; + } + for (int i = 0; i < n; i++) { + vint32mf2_t v; + *(vint32mf2_t*)(out + i + 7000) = v; + } + for (int i = 0; i < n; i++) { + vint64m1_t v; + *(vint64m1_t*)(out + i + 8000) = v; + } + for (int i = 0; i < n; i++) { + vint8mf8_t v; + *(vint8mf8_t*)(out + i + 9000) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c new file mode 100644 index 00000000000..42930b6af0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond) +{ + for (int i = 0; i < n; i++) { + vint16mf4_t v; + *(vint16mf4_t*)(out + i + 700) = v; + } + for (int i = 0; i < n; i++) { + a[i] = a[i] + b[i]; + } + for (int i = 0; i < n; i++) { + a[i] = a[i] * b[i]; + } + for (int i = 0; i < n; i++) { + a[i] = a[i] - b[i]; + } + for (int i = 0; i < n; i++) { + vint32mf2_t v; + *(vint32mf2_t*)(out + i + 7000) = v; + } + for (int i = 0; i < n; i++) { + vint16mf2_t v; + *(vint16mf2_t*)(out + i + 777) = v; + } + for (int i = 0; i < n; i++) { + vint64m1_t v; + *(vint64m1_t*)(out + i + 8000) = v; + } + for (int i = 0; i < n; i++) { + vfloat32mf2_t v; + *(vfloat32mf2_t*)(out + i + 7777) = v; + } + for (int i = 0; i < n; i++) { + vuint16mf2_t v; + *(vuint16mf2_t*)(out + i + 888) = v; + } + for (int i = 0; i < n; i++) { + vint8mf8_t v; + *(vint8mf8_t*)(out + i + 9000) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c new file mode 100644 index 00000000000..087d97c0a6e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond) +{ + for (int i = 0; i < n; i++) { + vint16mf4_t v; + *(vint16mf4_t*)(out + i + 700) = v; + } + for (int i = 0; i < n; i++) { + a[i] = a[i] + b[i]; + } + for (int i = 0; i < n; i++) { + a[i] = a[i] * b[i]; + } + for (int i = 0; i < n; i++) { + a[i] = a[i] - b[i]; + } + for (int i = 0; i < n; i++) { + vint32mf2_t v; + *(vint32mf2_t*)(out + i + 7000) = v; + } + for (int i = 0; i < n; i++) { + vint16mf2_t v; + *(vint16mf2_t*)(out + i + 777) = v; + } + for (int i = 0; i < n; i++) { + vint64m1_t v; + *(vint64m1_t*)(out + i + 8000) = v; + } + if (cond == 0) { + vbool64_t v; + *(vbool64_t*)(out + 1234) = v; + } else { + vuint8mf8_t v; + *(vuint8mf8_t*)(out + 5432) = v; + } + for (int i = 0; i < n; i++) { + vfloat32mf2_t v; + *(vfloat32mf2_t*)(out + i + 7777) = v; + } + for (int i = 0; i < n; i++) { + vuint16mf2_t v; + *(vuint16mf2_t*)(out + i + 888) = v; + } + for (int i = 0; i < n; i++) { + vint8mf8_t v; + *(vint8mf8_t*)(out + i + 9000) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c new file mode 100644 index 00000000000..8bb6cbe7c35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int n) +{ + vint8mf8_t v1 = *(vint8mf8_t*)(in + 1); + vint16mf4_t v2 = *(vint16mf4_t*)(in + 2); + vint32mf2_t v3 = *(vint32mf2_t*)(in + 3); + vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4); + + *(vint8mf8_t*)(out + 1) = v1; + *(vint16mf4_t*)(out + 2) = v2; + *(vint32mf2_t*)(out + 3) = v3; + *(vfloat32mf2_t*)(out + 4) = v4; + + for (int i = 0; i < n; i++) + { + vint16mf4_t v = *(vint16mf4_t*)(in + i + 5); + *(vint16mf4_t*)(out + i + 5) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c new file mode 100644 index 00000000000..30c2e061c13 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int n) +{ + vint8mf8_t v1 = *(vint8mf8_t*)(in + 1); + vint16mf4_t v2 = *(vint16mf4_t*)(in + 2); + vint32mf2_t v3 = *(vint32mf2_t*)(in + 3); + vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4); + + *(vint8mf8_t*)(out + 1) = v1; + *(vint16mf4_t*)(out + 2) = v2; + *(vint32mf2_t*)(out + 3) = v3; + *(vfloat32mf2_t*)(out + 4) = v4; + + for (int i = 0; i < n; i++) + { + vint16mf2_t v = *(vint16mf2_t*)(in + i + 5); + *(vint16mf2_t*)(out + i + 5) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c new file mode 100644 index 00000000000..7258f3f1606 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int n) +{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000); + *(vfloat32mf2_t*)(out + 10000) = v; + for (int i = 0; i < n; i++) + { + vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 1); + vint32mf2_t v2 = *(vint32mf2_t*)(in + i + 2); + *(vint16mf2_t*)(out + i + 1) = v1; + *(vint32mf2_t*)(out + i + 2) = v2; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c new file mode 100644 index 00000000000..7258f3f1606 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int n) +{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000); + *(vfloat32mf2_t*)(out + 10000) = v; + for (int i = 0; i < n; i++) + { + vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 1); + vint32mf2_t v2 = *(vint32mf2_t*)(in + i + 2); + *(vint16mf2_t*)(out + i + 1) = v1; + *(vint32mf2_t*)(out + i + 2) = v2; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c new file mode 100644 index 00000000000..32716591cde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +void foo (void * restrict in, void * restrict out, int n) +{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000); + *(vfloat32mf2_t*)(out + 10000) = v; + for (int i = 0; i < n; i++) + { + vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100); + + vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200); + vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300); + vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400); + vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500); + vbool1_t v5 = *(vbool1_t*)(in + i + 600); + + vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700); + + *(vint32mf2_t*)(out + i + 100) = v0; + *(vint16mf2_t*)(out + i + 200) = v1; + *(vint8mf2_t*)(out + i + 300) = v2; + *(vint8mf4_t*)(out + i + 400) = v3; + *(vint8mf8_t*)(out + i + 500) = v4; + *(vbool1_t*)(out + i + 600) = v5; + *(vint32mf2_t*)(out + i + 700) = v6; + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c new file mode 100644 index 00000000000..ea91f0e966a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void foo (int8_t * restrict in, int8_t * restrict out, int n) +{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000); + *(vfloat32mf2_t*)(out + 10000) = v; + + for (int i = 0 ; i < n * n; i++) + out[i] = out[i] + out[i]; + + for (int i = 0 ; i < n * n * n; i++) + out[i] = out[i] * out[i]; + + for (int i = 0 ; i < n * n * n * n; i++) + out[i] = out[i] * out[i]; + + for (int i = 0; i < n; i++) + { + vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100); + + vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200); + vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300); + vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400); + vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500); + vbool1_t v5 = *(vbool1_t*)(in + i + 600); + + vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700); + + *(vint32mf2_t*)(out + i + 100) = v0; + *(vint16mf2_t*)(out + i + 200) = v1; + *(vint8mf2_t*)(out + i + 300) = v2; + *(vint8mf4_t*)(out + i + 400) = v3; + *(vint8mf8_t*)(out + i + 500) = v4; + *(vbool1_t*)(out + i + 600) = v5; + *(vint32mf2_t*)(out + i + 700) = v6; + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c new file mode 100644 index 00000000000..7537bfe925d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond) +{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000); + *(vfloat32mf2_t*)(out + 10000) = v; + + if (cond) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 20000); + *(vfloat32mf2_t*)(out + 20000) = v; + } + else + { + vint16mf4_t v = *(vint16mf4_t*)(in + 20000); + *(vint16mf4_t*)(out + 20000) = v; + } + + for (int i = 0; i < n; i++) + { + vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100); + + vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200); + vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300); + vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400); + vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500); + vbool1_t v5 = *(vbool1_t*)(in + i + 600); + + vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700); + + *(vint32mf2_t*)(out + i + 100) = v0; + *(vint16mf2_t*)(out + i + 200) = v1; + *(vint8mf2_t*)(out + i + 300) = v2; + *(vint8mf4_t*)(out + i + 400) = v3; + *(vint8mf8_t*)(out + i + 500) = v4; + *(vbool1_t*)(out + i + 600) = v5; + *(vint32mf2_t*)(out + i + 700) = v6; + } +} +/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c new file mode 100644 index 00000000000..7537bfe925d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond) +{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000); + *(vfloat32mf2_t*)(out + 10000) = v; + + if (cond) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 20000); + *(vfloat32mf2_t*)(out + 20000) = v; + } + else + { + vint16mf4_t v = *(vint16mf4_t*)(in + 20000); + *(vint16mf4_t*)(out + 20000) = v; + } + + for (int i = 0; i < n; i++) + { + vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100); + + vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200); + vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300); + vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400); + vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500); + vbool1_t v5 = *(vbool1_t*)(in + i + 600); + + vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700); + + *(vint32mf2_t*)(out + i + 100) = v0; + *(vint16mf2_t*)(out + i + 200) = v1; + *(vint8mf2_t*)(out + i + 300) = v2; + *(vint8mf4_t*)(out + i + 400) = v3; + *(vint8mf8_t*)(out + i + 500) = v4; + *(vbool1_t*)(out + i + 600) = v5; + *(vint32mf2_t*)(out + i + 700) = v6; + } +} +/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */