From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1035) id DC9183858D1E; Mon, 19 Dec 2022 15:04:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DC9183858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1671462240; bh=K0W/62Y6cMoNAD8D2hWwfDk9a8KN6PQ+2SGYU9rwkYE=; h=From:To:Subject:Date:From; b=irGlOY8j7wjsUtUV3cMdxoQc2EyFvbSI4EgPc1VavTz880mo8T+HElGK1GjZqpa5S 4lmKouQHou0W2uKYovE2lxEo0vs0cTS4PstiNoX+FUr6F2oQzy5SSMiz9C2ZvpEvJb aKSGbepKC2TosRdRGNgPdmyFN9R1mHLP9AV5Bo94= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Richard Earnshaw To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4793] arm: correctly define __ARM_FEATURE_CLZ X-Act-Checkin: gcc X-Git-Author: Richard Earnshaw X-Git-Refname: refs/heads/master X-Git-Oldrev: 8577356f4b8a2c9a397390339006eca8f6efa14d X-Git-Newrev: aa510619f8b650322c113d8593dd57afe6c6f9ae Message-Id: <20221219150400.DC9183858D1E@sourceware.org> Date: Mon, 19 Dec 2022 15:04:00 +0000 (GMT) List-Id: https://gcc.gnu.org/g:aa510619f8b650322c113d8593dd57afe6c6f9ae commit r13-4793-gaa510619f8b650322c113d8593dd57afe6c6f9ae Author: Richard Earnshaw Date: Mon Dec 19 15:01:49 2022 +0000 arm: correctly define __ARM_FEATURE_CLZ The ACLE requires that __ARM_FEATURE_CLZ be defined if the hardware supports it; it's also clear that this doesn't mean the current ISA, so we must define this even when compiling for Thumb1 if the target supports CLZ in A32. This brings GCC into alignment with Clang. gcc/ChangeLog: * config/arm/arm-c.cc (__ARM_FEATURE_CLZ): Fix definition of preprocessor macro when target has CLZ in another ISA. Diff: --- gcc/config/arm/arm-c.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc index 86c56bf2680..202898fa041 100644 --- a/gcc/config/arm/arm-c.cc +++ b/gcc/config/arm/arm-c.cc @@ -238,8 +238,12 @@ arm_cpu_builtins (struct cpp_reader* pfile) builtin_define_with_int_value ("__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); + /* ACLE says that __ARM_FEATURE_CLZ is defined if the hardware + supports it; it's also clear that this doesn't mean the current + ISA, so we define this even when compiling for Thumb1 if the + target supports CLZ in A32. */ def_or_undef_macro (pfile, "__ARM_FEATURE_CLZ", - ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) + ((TARGET_ARM_ARCH >= 5 && arm_arch_notm) || TARGET_ARM_ARCH_ISA_THUMB >=2)); def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",