From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 74D1C3858D39; Sat, 7 Jan 2023 01:31:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 74D1C3858D39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1673055093; bh=UM5iyPaWykXRpEcDgRhTvZ7Mly/59GImbAfKd7PU/qc=; h=From:To:Subject:Date:From; b=QLAF0HQTzqrV9Ig14xNRoMbfS9yZAjGhl851JiZp4p3VXywOUarEmGRwYVsxabyNW UCw0wo8GzEmz7XcWQzaSpAiYyzaCqqELgr38RZnYzL7QUVPjJQTqIeRRrW9aQYGBzl fKsz2RPcuXuA4UlrAkdoKKjwb9L8+AQvlo6yyTWQ= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work104)] Update float 128-bit conversions, PR target/107299. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work104 X-Git-Oldrev: 26c6a5428e8b0485c28c3fa83777ed51e92cb357 X-Git-Newrev: 7405b2ad14cc37ba69d7b65cb8ec9f6874daba4b Message-Id: <20230107013133.74D1C3858D39@sourceware.org> Date: Sat, 7 Jan 2023 01:31:33 +0000 (GMT) List-Id: https://gcc.gnu.org/g:7405b2ad14cc37ba69d7b65cb8ec9f6874daba4b commit 7405b2ad14cc37ba69d7b65cb8ec9f6874daba4b Author: Michael Meissner Date: Fri Jan 6 20:31:07 2023 -0500 Update float 128-bit conversions, PR target/107299. This patch fixes two tests that are still failing when long double is IEEE 128-bit after the previous 2 patches for PR target/107299 have been applied. The tests are: gcc.target/powerpc/convert-fp-128.c gcc.target/powerpc/pr85657-3.c This patch is a rewrite of the patch submitted on August 18th: | https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599988.html This patch reworks the conversions between 128-bit binary floating point types. Previously, we would call rs6000_expand_float128_convert to do all conversions. Now, we only define the conversions between the same representation that turn into a NOP. The appropriate extend or truncate insn is generated, and after register allocation, it is converted to a move. This patch also fixes two places where we want to override the external name for the conversion function, and the wrong optab was used. Previously, rs6000_expand_float128_convert would handle the move or generate the call as needed. Now, it lets the machine independent code generate the call. But if we use the machine independent code to generate the call, we need to update the name for two optabs where a truncate would be used in terms of converting between the modes. This patch updates those two optabs. This patch was previously submitted on December 14th, 2022. This patch changes one built-in function from a FLOAT_TRUNCATE to a FLOAT_EXTEND, which is needed by the previous patch to genmodes.cc to allow allow the same precision to be used for various modes. 2022-01-06 Michael Meissner gcc/ PR target/107299 * config/rs6000/rs6000.cc (init_float128_ieee): Use the correct float_extend or float_truncate optab based on how the machine converts between IEEE 128-bit and IBM 128-bit. * config/rs6000/rs6000.md (IFKF): Delete. (IFKF_reg): Delete. (extendiftf2): Rewrite to be a move if IFmode and TFmode are both IBM 128-bit. Do not run if TFmode is IEEE 128-bit. (extendifkf2): Delete. (extendtfkf2): Delete. (extendtfif2): Delete. (trunciftf2): Delete. (truncifkf2): Delete. (trunckftf2): Delete. (extendkftf2): Implement conversion of IEEE 128-bit types as a move. (trunctfif2): Delete. (trunctfkf2): Implement conversion of IEEE 128-bit types as a move. (extendtf2_internal): Delete. (extendtf2_internal): Delete. Diff: --- gcc/config/rs6000/rs6000.cc | 2 +- gcc/config/rs6000/rs6000.md | 177 ++++++++++++-------------------------------- 2 files changed, 49 insertions(+), 130 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 3c6f9b81a99..6bb38c9c1d5 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -11175,7 +11175,7 @@ init_float128_ieee (machine_mode mode) if (mode != TFmode && FLOAT128_IBM_P (TFmode)) set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2"); - set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2"); + set_conv_libfunc (sext_optab, IFmode, mode, "__extendkftf2"); if (mode != TFmode && FLOAT128_IBM_P (TFmode)) set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2"); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3cae64a264a..203d0ba6a7f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -543,12 +543,6 @@ ; Iterator for 128-bit VSX types for pack/unpack (define_mode_iterator FMOVE128_VSX [V1TI KF]) -; Iterators for converting to/from TFmode -(define_mode_iterator IFKF [IF KF]) - -; Constraints for moving IF/KFmode. -(define_mode_attr IFKF_reg [(IF "d") (KF "wa")]) - ; Whether a floating point move is ok, don't allow SD without hardware FP (define_mode_attr fmove_ok [(SF "") (DF "") @@ -9161,106 +9155,65 @@ "xxlor %x0,%x1,%x2" [(set_attr "type" "veclogical")]) -;; Float128 conversion functions. These expand to library function calls. -;; We use expand to convert from IBM double double to IEEE 128-bit -;; and trunc for the opposite. -(define_expand "extendiftf2" - [(set (match_operand:TF 0 "gpc_reg_operand") - (float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" -{ - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) - -(define_expand "extendifkf2" - [(set (match_operand:KF 0 "gpc_reg_operand") - (float_extend:KF (match_operand:IF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" -{ - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) - -(define_expand "extendtfkf2" - [(set (match_operand:KF 0 "gpc_reg_operand") - (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" -{ - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) - -(define_expand "extendtfif2" - [(set (match_operand:IF 0 "gpc_reg_operand") - (float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" -{ - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) - -(define_expand "trunciftf2" - [(set (match_operand:TF 0 "gpc_reg_operand") - (float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" -{ - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) - -(define_expand "truncifkf2" - [(set (match_operand:KF 0 "gpc_reg_operand") - (float_truncate:KF (match_operand:IF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" -{ - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) - -(define_expand "trunckftf2" - [(set (match_operand:TF 0 "gpc_reg_operand") - (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" +;; Float128 conversion functions. We only define the 'conversions' between two +;; formats that use the same representation. We call the library function to +;; convert between IEEE 128-bit and IBM 128-bit. We can't do these moves by +;; using a SUBREG before register allocation. We set up the moves to prefer +;; the output register being the same as the input register, which would enable +;; the move to be deleted completely. +(define_insn_and_split "extendkftf2" + [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa") + (float_extend:TF (match_operand:KF 1 "gpc_reg_operand" "0,wa")))] + "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)" + "#" + "&& reload_completed" + [(set (match_dup 0) + (match_dup 2))] { - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) + operands[2] = gen_lowpart (TFmode, operands[1]); +} + [(set_attr "type" "veclogical")]) -(define_expand "trunctfif2" - [(set (match_operand:IF 0 "gpc_reg_operand") - (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" +(define_insn_and_split "trunctfkf2" + [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa") + (float_truncate:KF (match_operand:TF 1 "gpc_reg_operand" "0,wa")))] + "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)" + "#" + "&& reload_completed" + [(set (match_dup 0) + (match_dup 2))] { - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) + operands[2] = gen_lowpart (KFmode, operands[1]); +} + [(set_attr "type" "veclogical")]) -(define_insn_and_split "*extendtf2_internal" - [(set (match_operand:TF 0 "gpc_reg_operand" "=") - (float_extend:TF - (match_operand:IFKF 1 "gpc_reg_operand" "")))] - "TARGET_FLOAT128_TYPE - && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (mode)" +(define_insn_and_split "extendtfif2" + [(set (match_operand:IF 0 "gpc_reg_operand" "=wa,wa,r,r") + (float_extend:IF (match_operand:TF 1 "gpc_reg_operand" "0,wa,0,r")))] + "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)" "#" "&& reload_completed" - [(set (match_dup 0) (match_dup 2))] + [(set (match_dup 0) + (match_dup 2))] { - operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1])); -}) + operands[2] = gen_lowpart (IFmode, operands[1]); +} + [(set_attr "num_insns" "2") + (set_attr "length" "8")]) -(define_insn_and_split "*extendtf2_internal" - [(set (match_operand:IFKF 0 "gpc_reg_operand" "=") - (float_extend:IFKF - (match_operand:TF 1 "gpc_reg_operand" "")))] - "TARGET_FLOAT128_TYPE - && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (mode)" +(define_insn_and_split "extendiftf2" + [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa,r,r") + (float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "0,wa,0,r")))] + "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)" "#" "&& reload_completed" - [(set (match_dup 0) (match_dup 2))] + [(set (match_dup 0) + (match_dup 2))] { - operands[2] = gen_rtx_REG (mode, REGNO (operands[1])); -}) + operands[2] = gen_lowpart (TFmode, operands[1]); +} + [(set_attr "num_insns" "2") + (set_attr "length" "8")]) ;; Reload helper functions used by rs6000_secondary_reload. The patterns all @@ -14983,40 +14936,6 @@ [(set_attr "type" "vecfloat") (set_attr "size" "128")]) -;; Conversion between KFmode and TFmode if TFmode is ieee 128-bit floating -;; point is a simple copy. -(define_insn_and_split "extendkftf2" - [(set (match_operand:TF 0 "vsx_register_operand" "=wa,?wa") - (float_extend:TF (match_operand:KF 1 "vsx_register_operand" "0,wa")))] - "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD" - "@ - # - xxlor %x0,%x1,%x1" - "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" - [(const_int 0)] -{ - emit_note (NOTE_INSN_DELETED); - DONE; -} - [(set_attr "type" "*,veclogical") - (set_attr "length" "0,4")]) - -(define_insn_and_split "trunctfkf2" - [(set (match_operand:KF 0 "vsx_register_operand" "=wa,?wa") - (float_extend:KF (match_operand:TF 1 "vsx_register_operand" "0,wa")))] - "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD" - "@ - # - xxlor %x0,%x1,%x1" - "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" - [(const_int 0)] -{ - emit_note (NOTE_INSN_DELETED); - DONE; -} - [(set_attr "type" "*,veclogical") - (set_attr "length" "0,4")]) - (define_insn "truncdf2_hw" [(set (match_operand:DF 0 "altivec_register_operand" "=v") (float_truncate:DF