From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2140) id 3C1DE3858C50; Sat, 14 Jan 2023 00:16:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3C1DE3858C50 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1673655400; bh=vXA5JTaxtgZ8VurEXFqcgDqIY4hSv9cvZF+C60YrwcQ=; h=From:To:Subject:Date:From; b=Wk5yWlWm1X2cW9R22S7PcZtrJG58F5Mv9FGkplPhZdSTWsEIeK9cIItPoKinrS6LN Moj33sMEatSP0efhwlF/QYRJsWNAb6+d0/6PYLGkM+fjWP0wkaiUBBeBf5zbJQGC7+ zmdldW6Zf5j0Ckbvixm/PaKmoScyYEMUpl+4KxJw= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Alexandre Oliva To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5160] [PR40457] [arm] expand SI-aligned movdi into pair of movsi X-Act-Checkin: gcc X-Git-Author: Alexandre Oliva X-Git-Refname: refs/heads/master X-Git-Oldrev: ccd4df81aa6537c3c935b026905f6e2fd839654e X-Git-Newrev: acddf6665f067bc98a2529a699b1d4509a7387cb Message-Id: <20230114001640.3C1DE3858C50@sourceware.org> Date: Sat, 14 Jan 2023 00:16:39 +0000 (GMT) List-Id: https://gcc.gnu.org/g:acddf6665f067bc98a2529a699b1d4509a7387cb commit r13-5160-gacddf6665f067bc98a2529a699b1d4509a7387cb Author: Alexandre Oliva Date: Fri Jan 13 21:15:41 2023 -0300 [PR40457] [arm] expand SI-aligned movdi into pair of movsi When expanding a misaligned DImode move, emit aligned SImode moves if the parts are sufficiently aligned. This enables neighboring stores to be peephole-combined into stm, as expected by the PR40457 testcase, even after SLP vectorizes the originally aligned SImode stores into a misaligned DImode store. for gcc/ChangeLog PR target/40457 * config/arm/arm.md (movmisaligndi): Prefer aligned SImode moves. Diff: --- gcc/config/arm/arm.md | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 31dfea10af1..3710c5cac56 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12783,8 +12783,16 @@ rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]); rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]); - emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); - emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + if (aligned_operand (lo_op0, SImode) && aligned_operand (lo_op1, SImode)) + { + emit_move_insn (lo_op0, lo_op1); + emit_move_insn (hi_op0, hi_op1); + } + else + { + emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); + emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + } DONE; })