From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2140) id B1B9438493CB; Sat, 14 Jan 2023 12:11:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B1B9438493CB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1673698292; bh=xf+DwrSOftP1VCgkihttrMRiPopfCDEe8kPdTKYNvfY=; h=From:To:Subject:Date:From; b=dz5UUB1LLkpcY2QBeddypnP+YETS0Csm4Z6sx30T7DnUCE3zDSAg+pBDXKOuOFQB1 5PCaMNf3HdozFiHICTvjqSDu3CUbTEfpeE+4X4i747dtUZ3TehdKB2gX1q6oUggs+8 yNCKXNLgNdF35G0YadJkNKUmNCmmWPcSOWHvg0AE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Alexandre Oliva To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/aoliva/heads/testme)] [PR106746] drop cselib addr lookup in debug insn mem X-Act-Checkin: gcc X-Git-Author: Alexandre Oliva X-Git-Refname: refs/users/aoliva/heads/testme X-Git-Oldrev: 88679960c2665d87c8354ce35a48aaadbe3f0793 X-Git-Newrev: d8d14963f7eb24e07a4c066909db734e31ec8736 Message-Id: <20230114121132.B1B9438493CB@sourceware.org> Date: Sat, 14 Jan 2023 12:11:32 +0000 (GMT) List-Id: https://gcc.gnu.org/g:d8d14963f7eb24e07a4c066909db734e31ec8736 commit d8d14963f7eb24e07a4c066909db734e31ec8736 Author: Alexandre Oliva Date: Sat Jan 14 05:33:40 2023 -0300 [PR106746] drop cselib addr lookup in debug insn mem The testcase used to get scheduled differently depending on the presence of debug insns with MEMs. It's not clear to me why those MEMs affected scheduling, but the cselib pre-canonicalization of the MEM address is not used at all when analyzing debug insns, so the memory allocation and lookup are pure waste. Somehow, avoiding that waste fixes the problem, or makes it go latent. for gcc/ChangeLog PR debug/106746 * sched-deps.cc (sched_analyze_2): Skip cselib address lookup within debug insns. for gcc/testsuite/ChangeLog PR debug/106746 * gcc.dg/target/i386/pr106746.c: New. Diff: --- gcc/sched-deps.cc | 36 ++++++++++++++++---------------- gcc/testsuite/gcc.target/i386/pr106746.c | 29 +++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 18 deletions(-) diff --git a/gcc/sched-deps.cc b/gcc/sched-deps.cc index f9371b81fb4..a9214f67432 100644 --- a/gcc/sched-deps.cc +++ b/gcc/sched-deps.cc @@ -2605,26 +2605,26 @@ sched_analyze_2 (class deps_desc *deps, rtx x, rtx_insn *insn) case MEM: { - /* Reading memory. */ - rtx_insn_list *u; - rtx_insn_list *pending; - rtx_expr_list *pending_mem; - rtx t = x; - - if (sched_deps_info->use_cselib) - { - machine_mode address_mode = get_address_mode (t); - - t = shallow_copy_rtx (t); - cselib_lookup_from_insn (XEXP (t, 0), address_mode, 1, - GET_MODE (t), insn); - XEXP (t, 0) - = cselib_subst_to_values_from_insn (XEXP (t, 0), GET_MODE (t), - insn); - } - if (!DEBUG_INSN_P (insn)) { + /* Reading memory. */ + rtx_insn_list *u; + rtx_insn_list *pending; + rtx_expr_list *pending_mem; + rtx t = x; + + if (sched_deps_info->use_cselib) + { + machine_mode address_mode = get_address_mode (t); + + t = shallow_copy_rtx (t); + cselib_lookup_from_insn (XEXP (t, 0), address_mode, 1, + GET_MODE (t), insn); + XEXP (t, 0) + = cselib_subst_to_values_from_insn (XEXP (t, 0), GET_MODE (t), + insn); + } + t = canon_rtx (t); pending = deps->pending_read_insns; pending_mem = deps->pending_read_mems; diff --git a/gcc/testsuite/gcc.target/i386/pr106746.c b/gcc/testsuite/gcc.target/i386/pr106746.c new file mode 100644 index 00000000000..14f7dab71d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106746.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fsched2-use-superblocks -fcompare-debug -Wno-psabi" } */ + +typedef char __attribute__((__vector_size__ (64))) U; +typedef short __attribute__((__vector_size__ (64))) V; +typedef int __attribute__((__vector_size__ (64))) W; + +char c; +U a; +U *r; +W foo0_v512u32_0; + +void +foo (W) +{ + U u; + V v; + W w = __builtin_shuffle (foo0_v512u32_0, foo0_v512u32_0); + u = + __builtin_shufflevector (a, u, 3, 0, 4, 9, 9, 6, 7, 8, 5, + 0, 6, 1, 8, 1, 2, 8, 6, + 1, 8, 4, 9, 3, 8, 4, 6, 0, 9, 0, 1, 8, 2, 3, 3, + 0, 4, 9, 9, 6, 7, 8, 5, + 0, 6, 1, 8, 1, 2, 8, 6, + 1, 8, 4, 9, 3, 8, 4, 6, 0, 9, 0, 1, 8, 2, 3); + v *= c; + w &= c; + *r = (U) v + (U) w; +}