From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2140) id CDFF03858D28; Thu, 19 Jan 2023 04:12:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CDFF03858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1674101568; bh=qFmwm0bDyp+wasYo9w5oLhGJ4vBIpFgx5AwRgaTGLDE=; h=From:To:Subject:Date:From; b=JJGm016HHDfzmVDssdPXJJO6/3umd0c2KVCT5TnIdLUtuyqARrTd09abR6bPV0Vjf X/Ls6tP/OffNCcvp62WusCzY64gsq6cXdy/AhjrfhBfuI7cUGiKlOgFn7j2HSh9eIv RxoFS7l6ZfTzPPxxcfGDt2EfvAWbsng/vGS/SRS0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Alexandre Oliva To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5252] [PR106746] drop cselib addr lookup in debug insn mem X-Act-Checkin: gcc X-Git-Author: Alexandre Oliva X-Git-Refname: refs/heads/master X-Git-Oldrev: 9f98cfa51b416a2b40884b7d5202eb4daa801ec0 X-Git-Newrev: 3c99493bf39a7fef9213e6f5af94b78bb15fcfdc Message-Id: <20230119041248.CDFF03858D28@sourceware.org> Date: Thu, 19 Jan 2023 04:12:48 +0000 (GMT) List-Id: https://gcc.gnu.org/g:3c99493bf39a7fef9213e6f5af94b78bb15fcfdc commit r13-5252-g3c99493bf39a7fef9213e6f5af94b78bb15fcfdc Author: Alexandre Oliva Date: Thu Jan 19 01:09:15 2023 -0300 [PR106746] drop cselib addr lookup in debug insn mem The testcase used to get scheduled differently depending on the presence of debug insns with MEMs. It's not clear to me why those MEMs affected scheduling, but the cselib pre-canonicalization of the MEM address is not used at all when analyzing debug insns, so the memory allocation and lookup are pure waste. Somehow, avoiding that waste fixes the problem, or makes it go latent. for gcc/ChangeLog PR debug/106746 * sched-deps.cc (sched_analyze_2): Skip cselib address lookup within debug insns. for gcc/testsuite/ChangeLog PR debug/106746 * gcc.target/i386/pr106746.c: New. Diff: --- gcc/sched-deps.cc | 36 ++++++++++++++++---------------- gcc/testsuite/gcc.target/i386/pr106746.c | 29 +++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 18 deletions(-) diff --git a/gcc/sched-deps.cc b/gcc/sched-deps.cc index f9371b81fb4..a9214f67432 100644 --- a/gcc/sched-deps.cc +++ b/gcc/sched-deps.cc @@ -2605,26 +2605,26 @@ sched_analyze_2 (class deps_desc *deps, rtx x, rtx_insn *insn) case MEM: { - /* Reading memory. */ - rtx_insn_list *u; - rtx_insn_list *pending; - rtx_expr_list *pending_mem; - rtx t = x; - - if (sched_deps_info->use_cselib) - { - machine_mode address_mode = get_address_mode (t); - - t = shallow_copy_rtx (t); - cselib_lookup_from_insn (XEXP (t, 0), address_mode, 1, - GET_MODE (t), insn); - XEXP (t, 0) - = cselib_subst_to_values_from_insn (XEXP (t, 0), GET_MODE (t), - insn); - } - if (!DEBUG_INSN_P (insn)) { + /* Reading memory. */ + rtx_insn_list *u; + rtx_insn_list *pending; + rtx_expr_list *pending_mem; + rtx t = x; + + if (sched_deps_info->use_cselib) + { + machine_mode address_mode = get_address_mode (t); + + t = shallow_copy_rtx (t); + cselib_lookup_from_insn (XEXP (t, 0), address_mode, 1, + GET_MODE (t), insn); + XEXP (t, 0) + = cselib_subst_to_values_from_insn (XEXP (t, 0), GET_MODE (t), + insn); + } + t = canon_rtx (t); pending = deps->pending_read_insns; pending_mem = deps->pending_read_mems; diff --git a/gcc/testsuite/gcc.target/i386/pr106746.c b/gcc/testsuite/gcc.target/i386/pr106746.c new file mode 100644 index 00000000000..14f7dab71d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106746.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fsched2-use-superblocks -fcompare-debug -Wno-psabi" } */ + +typedef char __attribute__((__vector_size__ (64))) U; +typedef short __attribute__((__vector_size__ (64))) V; +typedef int __attribute__((__vector_size__ (64))) W; + +char c; +U a; +U *r; +W foo0_v512u32_0; + +void +foo (W) +{ + U u; + V v; + W w = __builtin_shuffle (foo0_v512u32_0, foo0_v512u32_0); + u = + __builtin_shufflevector (a, u, 3, 0, 4, 9, 9, 6, 7, 8, 5, + 0, 6, 1, 8, 1, 2, 8, 6, + 1, 8, 4, 9, 3, 8, 4, 6, 0, 9, 0, 1, 8, 2, 3, 3, + 0, 4, 9, 9, 6, 7, 8, 5, + 0, 6, 1, 8, 1, 2, 8, 6, + 1, 8, 4, 9, 3, 8, 4, 6, 0, 9, 0, 1, 8, 2, 3); + v *= c; + w &= c; + *r = (U) v + (U) w; +}