[gcc(refs/users/meissner/heads/dmf007)] PowerPC: Add -mcpu=future.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:1db7a5d62e4646d97325af6fa89ca70fbdbfa19d

commit 1db7a5d62e4646d97325af6fa89ca70fbdbfa19d
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Jan 20 17:43:18 2023 -0500

    PowerPC: Add -mcpu=future.
    
    This patch adds support for the -mcpu=future and -mtune=future options.
    Besides defining __ARCH_PWR_FUTURE__ this particular patch does not enable any
    new features.
    
    At present, we do not have any specific differences in terms of cpu tuning for
    future machines, so we make -mtune=future act the same as -mtune=power10.  It
    is anticipated that we may add support for changing the tuning characteristics
    for -mtune=future at a later time.
    
    These patches implement support for potential future PowerPC cpus.  At this
    time, features enabled with -mcpu=future may or may not be in actual PowerPCs
    that will be delivered in the future.
    
    The patches have been tested on the following platforms.  I added the patches
    for PR target/107299 that I submitted on November 2nd before doing the builds so
    that GCC would build on systems using IEEE 128-bit long double.
        *   https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604834.html
    
    There were no regressions with doing bootstrap builds and running the regression
    tests:
    
        1)  Power10 LE using --with-cpu=power10 --with-long-double-format=ieee;
        2)  Power10 LE using --with-cpu=power10 --with-long-double-format=ibm;
        3)  Power9 LE using --with-cpu=power9 --with-long-double-format=ibm; and
        4)  Power8 BE using --with-cpu=power8 (both 32-bit & 64-bit tested).
    
    Can I check this patch into the GCC 13 master branch?
    
    2023-01-20   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
            __ARCH_PWR_FUTURE__ if -mcpu=future.
            * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): New macro.
            (POWERPC_MASKS): Add -mfuture.
            * config/rs6000/rs6000-opts.h (enum processor_type): Add
            PROCESSOR_FUTURE.
            * config/rs6000/rs6000-tables.opt: Regenerate.
            * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
            -mcpu=future support.  Make -mtune=future act like -mtune=power10 for
            now.
            (rs6000_machine_from_flags): Likewise.
            (rs6000_reassociation_width): Likewise.
            (rs6000_adjust_cost): Likewise.
            (rs6000_issue_rate): Likewise.
            (rs6000_sched_reorder): Likewise.
            (rs6000_sched_reorder2): Likewise.
            (rs6000_register_move_cost): Likewise.
            (rs6000_opt_masks): Add -mfuture.
            * config/rs6000/rs6000.h (ASM_CPU_SUPPORT): Likewise.
            * config/rs6000/rs6000.opt (-mfuture): New undocumented debug switch.
            * config/rs6000/rs6000.md (cpu attribute): Add -mcpu=future support.
            * doc/invoke.texi (IBM RS/6000 and PowerPC Options): Document -mcpu=future.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc       |  2 ++
 gcc/config/rs6000/rs6000-cpus.def   |  6 ++++++
 gcc/config/rs6000/rs6000-opts.h     |  4 +++-
 gcc/config/rs6000/rs6000-tables.opt |  3 +++
 gcc/config/rs6000/rs6000.cc         | 27 +++++++++++++++++++++++----
 gcc/config/rs6000/rs6000.h          |  1 +
 gcc/config/rs6000/rs6000.md         |  2 +-
 gcc/config/rs6000/rs6000.opt        |  4 ++++
 gcc/doc/invoke.texi                 |  2 +-
 9 files changed, 44 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 8555174d36e..2803014f2b6 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,6 +447,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
   if ((flags & OPTION_MASK_POWER10) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+  if ((flags & OPTION_MASK_FUTURE) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 4f350da378c..deb4ea1c980 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,6 +86,10 @@
 				 | OPTION_MASK_POWER10			\
 				 | OTHER_POWER10_MASKS)
 
+/* Flags for a potential future processor that may or may not be delivered.  */
+#define ISA_FUTURE_MASKS	(ISA_3_1_MASKS_SERVER			\
+				 | OPTION_MASK_FUTURE)
+
 /* Flags that need to be turned off if -mno-power9-vector.  */
 #define OTHER_P9_VECTOR_MASKS	(OPTION_MASK_FLOAT128_HW		\
 				 | OPTION_MASK_P9_MINMAX)
@@ -132,6 +136,7 @@
 				 | OPTION_MASK_FPRND			\
 				 | OPTION_MASK_POWER10			\
 				 | OPTION_MASK_P10_FUSION		\
+				 | OPTION_MASK_FUTURE			\
 				 | OPTION_MASK_HTM			\
 				 | OPTION_MASK_ISEL			\
 				 | OPTION_MASK_MFCRF			\
@@ -263,3 +268,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
 	    | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
 RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 8040cfdc06e..f56f01d6fa5 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -67,7 +67,9 @@ enum processor_type
    PROCESSOR_MPCCORE,
    PROCESSOR_CELL,
    PROCESSOR_PPCA2,
-   PROCESSOR_TITAN
+   PROCESSOR_TITAN,
+
+   PROCESSOR_FUTURE
 };
 
 
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index b82f8205fa1..3ff28e39f6c 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -197,3 +197,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55)
 EnumValue
 Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
 
+EnumValue
+Enum(rs6000_cpu_opt_value) String(future) Value(57)
+
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7e76c37fdab..1a7d1d92687 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3761,6 +3761,10 @@ rs6000_option_override_internal (bool global_init_p)
   gcc_assert (tune_index >= 0);
   rs6000_tune = processor_target_table[tune_index].processor;
 
+  /* For now, make -mtune=future the same as -mtune=power10.  */
+  if (rs6000_tune == PROCESSOR_FUTURE)
+    rs6000_tune = PROCESSOR_POWER10;
+
   if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
       || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
       || rs6000_cpu == PROCESSOR_PPCE5500)
@@ -4430,6 +4434,7 @@ rs6000_option_override_internal (bool global_init_p)
 			&& rs6000_tune != PROCESSOR_POWER8
 			&& rs6000_tune != PROCESSOR_POWER9
 			&& rs6000_tune != PROCESSOR_POWER10
+			&& rs6000_tune != PROCESSOR_FUTURE
 			&& rs6000_tune != PROCESSOR_PPCA2
 			&& rs6000_tune != PROCESSOR_CELL
 			&& rs6000_tune != PROCESSOR_PPC476);
@@ -4444,6 +4449,7 @@ rs6000_option_override_internal (bool global_init_p)
 				 || rs6000_tune == PROCESSOR_POWER8
 				 || rs6000_tune == PROCESSOR_POWER9
 				 || rs6000_tune == PROCESSOR_POWER10
+				 || rs6000_tune == PROCESSOR_FUTURE
 				 || rs6000_tune == PROCESSOR_PPCE500MC
 				 || rs6000_tune == PROCESSOR_PPCE500MC64
 				 || rs6000_tune == PROCESSOR_PPCE5500
@@ -4743,6 +4749,7 @@ rs6000_option_override_internal (bool global_init_p)
 	break;
 
       case PROCESSOR_POWER10:
+      case PROCESSOR_FUTURE:
 	rs6000_cost = &power10_cost;
 	break;
 
@@ -5874,6 +5881,10 @@ rs6000_machine_from_flags (void)
   if (rs6000_cpu == PROCESSOR_MPCCORE)
     return "\"821\"";
 
+  /* Some future processor.  For now, just use power10.  */
+  if (rs6000_cpu == PROCESSOR_FUTURE)
+    return "future";
+
 #if 0
   /* This (and ppc64 below) are disabled here (for now at least) because
      PROCESSOR_POWERPC, PROCESSOR_POWERPC64, and PROCESSOR_COMMON
@@ -10113,6 +10124,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
     case PROCESSOR_POWER8:
     case PROCESSOR_POWER9:
     case PROCESSOR_POWER10:
+    case PROCESSOR_FUTURE:
       if (DECIMAL_FLOAT_MODE_P (mode))
 	return 1;
       if (VECTOR_MODE_P (mode))
@@ -17912,7 +17924,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
 
 	/* Separate a load from a narrower, dependent store.  */
 	if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
-	     || rs6000_tune == PROCESSOR_POWER10)
+	     || rs6000_tune == PROCESSOR_POWER10
+	     || rs6000_tune == PROCESSOR_FUTURE)
 	    && GET_CODE (PATTERN (insn)) == SET
 	    && GET_CODE (PATTERN (dep_insn)) == SET
 	    && MEM_P (XEXP (PATTERN (insn), 1))
@@ -17951,6 +17964,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
 		 || rs6000_tune == PROCESSOR_POWER8
 		 || rs6000_tune == PROCESSOR_POWER9
 		 || rs6000_tune == PROCESSOR_POWER10
+		 || rs6000_tune == PROCESSOR_FUTURE
                  || rs6000_tune == PROCESSOR_CELL)
                 && recog_memoized (dep_insn)
                 && (INSN_CODE (dep_insn) >= 0))
@@ -18525,6 +18539,7 @@ rs6000_issue_rate (void)
   case PROCESSOR_POWER9:
     return 6;
   case PROCESSOR_POWER10:
+  case PROCESSOR_FUTURE:
     return 8;
   default:
     return 1;
@@ -19241,7 +19256,8 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
     load_store_pendulum = 0;
 
   /* Do Power10 dependent reordering.  */
-  if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
+  if ((rs6000_tune == PROCESSOR_POWER10
+       || rs6000_tune == PROCESSOR_FUTURE) && last_scheduled_insn)
     power10_sched_reorder (ready, n_ready - 1);
 
   return rs6000_issue_rate ();
@@ -19266,7 +19282,8 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
     return power9_sched_reorder2 (ready, *pn_ready - 1);
 
   /* Do Power10 dependent reordering.  */
-  if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
+  if ((rs6000_tune == PROCESSOR_POWER10
+       || rs6000_tune == PROCESSOR_FUTURE) && last_scheduled_insn)
     return power10_sched_reorder (ready, *pn_ready - 1);
 
   return cached_can_issue_more;
@@ -22481,7 +22498,8 @@ rs6000_register_move_cost (machine_mode mode,
 		 allocation a move within the same class might turn
 		 out to be a nop.  */
 	      if (rs6000_tune == PROCESSOR_POWER9
-		  || rs6000_tune == PROCESSOR_POWER10)
+		  || rs6000_tune == PROCESSOR_POWER10
+		  || rs6000_tune == PROCESSOR_FUTURE)
 		ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
 	      else
 		ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
@@ -24139,6 +24157,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "float128-hardware",	OPTION_MASK_FLOAT128_HW,	false, true  },
   { "fprnd",			OPTION_MASK_FPRND,		false, true  },
   { "power10",			OPTION_MASK_POWER10,		false, true  },
+  { "future",			OPTION_MASK_FUTURE,		false, true  },
   { "hard-dfp",			OPTION_MASK_DFP,		false, true  },
   { "htm",			OPTION_MASK_HTM,		false, true  },
   { "isel",			OPTION_MASK_ISEL,		false, true  },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3503614efbd..44fa355a061 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -163,6 +163,7 @@
   mcpu=e5500: -me5500; \
   mcpu=e6500: -me6500; \
   mcpu=titan: -mtitan; \
+  mcpu=future: -mfuture; \
   !mcpu*: %{mpower9-vector: -mpower9; \
 	    mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \
 	    mvsx: -mpower7; \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4a7812fa592..5f933bede93 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -350,7 +350,7 @@
    ppc403,ppc405,ppc440,ppc476,
    ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
    power4,power5,power6,power7,power8,power9,power10,
-   rs64a,mpccore,cell,ppca2,titan"
+   rs64a,mpccore,cell,ppca2,titan,future"
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
 ;; The ISA we implement.
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index bde6d3ff664..04532a774b9 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -620,6 +620,10 @@ mieee128-constant
 Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
 Generate (do not generate) code that uses the LXVKQ instruction.
 
+mfuture
+Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags)
+Generate (do not generate) future instructions.
+
 ; Documented parameters
 
 -param=rs6000-vect-unroll-limit=
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 631c00582bf..423e5bb4d22 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -29140,7 +29140,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
 @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
 @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
 @samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
-@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
+@samp{powerpc64le}, @samp{rs64}, @samp{future}, and @samp{native}.
 
 @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
 @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either