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From: Andrea Corallo <akrl@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5357] arm: improve tests for vcmulq* Date: Wed, 25 Jan 2023 13:49:49 +0000 (GMT) [thread overview] Message-ID: <20230125134949.3A01C3858C31@sourceware.org> (raw) https://gcc.gnu.org/g:c3c828436e7db1787d644153fe07daf356c99f2a commit r13-5357-gc3c828436e7db1787d644153fe07daf356c99f2a Author: Andrea Corallo <andrea.corallo@arm.com> Date: Mon Nov 28 17:35:24 2022 +0100 arm: improve tests for vcmulq* gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Use check-function-bodies instead of scan-assembler checks. Use extern "C" for C++ testing. * gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise. Diff: --- .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 24 +++++++++++++-- .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 24 +++++++++++++-- .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 34 +++++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 34 +++++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 24 +++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 24 +++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 34 +++++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 34 +++++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 33 +++++++++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 33 +++++++++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 24 +++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 24 +++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 34 +++++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 34 +++++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 33 +++++++++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 33 +++++++++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 24 +++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 24 +++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 34 +++++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 34 +++++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 34 +++++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 34 +++++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 33 +++++++++++++++++++-- .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 33 +++++++++++++++++++-- 24 files changed, 656 insertions(+), 74 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c index 142c315ecf5..456370e1de1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vcmulq_f16 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +/* +**foo1: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vcmulq (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c index 158d750793d..64db652a1a1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vcmulq_f32 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +/* +**foo1: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vcmulq (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c index b38e0d9fb52..b60f5d718f8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c index 7bf68735e52..22157d4e58f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c index fc7162aaa9c..f01b0f3421f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vcmulq_rot180_f16 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +/* +**foo1: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vcmulq_rot180 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c index 13a4553b6bd..537385c5209 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vcmulq_rot180_f32 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +/* +**foo1: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vcmulq_rot180 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c index 8767e2beee8..bc8692eb043 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot180_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot180_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c index 3f951039f35..d2a0b6d3f2c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot180_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot180_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c index f8e835f158f..37d7b79a75c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot180_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot180_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c index d0d30c59d44..1e57fba4bd3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot180_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot180_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c index 225b8910f88..05c444af804 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vcmulq_rot270_f16 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +/* +**foo1: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vcmulq_rot270 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c index 1c8b0ebcf7e..b599c9fc171 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vcmulq_rot270_f32 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +/* +**foo1: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vcmulq_rot270 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c index 20ccb5e9423..fded8a05089 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot270_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot270_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c index 7499f4271a6..54d939eb378 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot270_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot270_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c index d1b52e74d6d..d1e58cb84bb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot270_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot270_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c index 35da5936f66..07c781f5103 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot270_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot270_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c index 17f96cb0a78..53b1930c045 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vcmulq_rot90_f16 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +/* +**foo1: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vcmulq_rot90 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c index 739fc9cd1fa..147f1807c29 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vcmulq_rot90_f32 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +/* +**foo1: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vcmulq_rot90 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c index 8259baa82cc..8c4b0902b09 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot90_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot90_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c index 751a9a6c03d..b3131a5e984 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot90_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot90_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c index c4aef6cbf30..000610367b9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot90_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot90_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c index 9c54f0870e7..8e31ad563c6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot90_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot90_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c index 7634d61b6ea..b53324738f2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c index 21b6acf9733..a73482a09e1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file
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