From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2092) id A11D23858416; Wed, 25 Jan 2023 13:50:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A11D23858416 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1674654650; bh=89OIU8crGfAsbytc0WlkyaNMhZcKWxzu7P/CbLsj3P0=; h=From:To:Subject:Date:From; b=BSDSCeYj4ytXvfafKZ8F8rxTw1rCCuSV/4prdEtie1+6tzss3UF906jVc7Rs5FnUz tDiVfi0tJxi26fT/yw8Lh7mA0z/HCKoh3bAOZlilJR/zmRwTP60VerrzkLBQ2LhG0D 4HgK5QRAm8dSL1+DfbzMc4Xbs/EBZvnMVYIt9jJs= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Andrea Corallo To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5369] arm: improve tests and fix vqnegq* X-Act-Checkin: gcc X-Git-Author: Andrea Corallo X-Git-Refname: refs/heads/master X-Git-Oldrev: 73a712e9c6620f8b7aede3eb1c2984fb91646201 X-Git-Newrev: 1563de6f9d3a9607ae2872b87d9718add3cf6e6a Message-Id: <20230125135050.A11D23858416@sourceware.org> Date: Wed, 25 Jan 2023 13:50:50 +0000 (GMT) List-Id: https://gcc.gnu.org/g:1563de6f9d3a9607ae2872b87d9718add3cf6e6a commit r13-5369-g1563de6f9d3a9607ae2872b87d9718add3cf6e6a Author: Andrea Corallo Date: Mon Nov 28 17:49:36 2022 +0100 arm: improve tests and fix vqnegq* gcc/ChangeLog: * config/arm/mve.md (mve_vqnegq_s): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c: Use check-function-bodies instead of scan-assembler checks. Use extern "C" for C++ testing. * gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise. Diff: --- gcc/config/arm/mve.md | 2 +- .../gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c | 33 ++++++++++++++++++++-- .../gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c | 33 ++++++++++++++++++++-- .../gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c | 33 ++++++++++++++++++++-- .../gcc.target/arm/mve/intrinsics/vqnegq_s16.c | 28 +++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vqnegq_s32.c | 24 ++++++++++++++-- .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 24 ++++++++++++++-- 7 files changed, 159 insertions(+), 18 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 27691a1e32c..555ad1b66c8 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -374,7 +374,7 @@ VQNEGQ_S)) ] "TARGET_HAVE_MVE" - "vqneg.s%# %q0, %q1" + "vqneg.s%#\t%q0, %q1" [(set_attr "type" "mve_move") ]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c index 4f0145d2ebd..f3799a35b12 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vqnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) { return vqnegq_m_s16 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vqnegt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vqnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) { return vqnegq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c index da4f90bad53..bbe64ff4d52 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vqnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) { return vqnegq_m_s32 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vqnegt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vqnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) { return vqnegq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c index ac1250b2fac..71fcdd7cba7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vqnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) { return vqnegq_m_s8 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vqnegt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vqnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) { return vqnegq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c index f9210cd70f4..d5fb4a19854 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c @@ -1,21 +1,41 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vqneg.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a) { return vqnegq_s16 (a); } -/* { dg-final { scan-assembler "vqneg.s16" } } */ +/* +**foo1: +** ... +** vqneg.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a) { return vqnegq (a); } -/* { dg-final { scan-assembler "vqneg.s16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c index c2ded7fe659..2c8e709f491 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vqneg.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a) { return vqnegq_s32 (a); } -/* { dg-final { scan-assembler "vqneg.s32" } } */ +/* +**foo1: +** ... +** vqneg.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a) { return vqnegq (a); } -/* { dg-final { scan-assembler "vqneg.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c index d1cc83a6cd0..2f7f7619ef6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vqneg.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a) { return vqnegq_s8 (a); } -/* { dg-final { scan-assembler "vqneg.s8" } } */ +/* +**foo1: +** ... +** vqneg.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a) { return vqnegq (a); } -/* { dg-final { scan-assembler "vqneg.s8" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file