From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 0AB503858416; Fri, 27 Jan 2023 09:35:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0AB503858416 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1674812151; bh=IH8Psgg/SeYSp1RWtb/wgd2MtG47OtGNmS7U2+bLR74=; h=From:To:Subject:Date:From; b=oSErlTjJTd4/naZ9HMLTMYKZwtb2aeV/G+2l3eQ1nowhoIQMgpXOKQT+0oOTPthEU PoXE1FGuIp8dIZQLf8cWnG6R5MuInmCdfZmcHQJ5YSf/7sVzebJNTfAbrK6QV/WvGv GY7bJ4MoX95NaNazW832v8B7zVnXNDnbGoMTb3RY= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5427] RISC-V: Fix incorrect attributes of vsetvl instructions pattern X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 83979240c072599bc8595a9324c3f4371eedbc7c X-Git-Newrev: e3bcf0726207185af88dd3c8fbed35b05cd80ddd Message-Id: <20230127093551.0AB503858416@sourceware.org> Date: Fri, 27 Jan 2023 09:35:51 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e3bcf0726207185af88dd3c8fbed35b05cd80ddd commit r13-5427-ge3bcf0726207185af88dd3c8fbed35b05cd80ddd Author: Ju-Zhe Zhong Date: Wed Jan 18 10:44:15 2023 +0800 RISC-V: Fix incorrect attributes of vsetvl instructions pattern gcc/ChangeLog: * config/riscv/vector.md: Fix incorrect attributes. Diff: --- gcc/config/riscv/vector.md | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 83bc1ab9c46..7d84f9eb3b7 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -95,13 +95,7 @@ (const_int 32) (eq_attr "mode" "VNx1DI,VNx2DI,VNx4DI,VNx8DI,\ VNx1DF,VNx2DF,VNx4DF,VNx8DF") - (const_int 64) - - (eq_attr "type" "vsetvl") - (if_then_else (eq_attr "INSN_CODE (curr_insn) == CODE_FOR_vsetvldi - || INSN_CODE (curr_insn) == CODE_FOR_vsetvlsi") - (symbol_ref "INTVAL (operands[2])") - (const_int INVALID_ATTRIBUTE))] + (const_int 64)] (const_int INVALID_ATTRIBUTE))) ;; Ditto to LMUL. @@ -149,12 +143,7 @@ (eq_attr "mode" "VNx4DI,VNx4DF") (symbol_ref "riscv_vector::get_vlmul(E_VNx4DImode)") (eq_attr "mode" "VNx8DI,VNx8DF") - (symbol_ref "riscv_vector::get_vlmul(E_VNx8DImode)") - (eq_attr "type" "vsetvl") - (if_then_else (eq_attr "INSN_CODE (curr_insn) == CODE_FOR_vsetvldi - || INSN_CODE (curr_insn) == CODE_FOR_vsetvlsi") - (symbol_ref "INTVAL (operands[3])") - (const_int INVALID_ATTRIBUTE))] + (symbol_ref "riscv_vector::get_vlmul(E_VNx8DImode)")] (const_int INVALID_ATTRIBUTE))) ;; It is valid for instruction that require sew/lmul ratio. @@ -551,7 +540,11 @@ "TARGET_VECTOR" "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5" [(set_attr "type" "vsetvl") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "sew") (symbol_ref "INTVAL (operands[2])")) + (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])")) + (set (attr "ta") (symbol_ref "INTVAL (operands[4])")) + (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))]) ;; vsetvl zero,zero,vtype instruction. ;; This pattern has no side effects and does not set X0 register. @@ -583,7 +576,11 @@ "TARGET_VECTOR" "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4" [(set_attr "type" "vsetvl") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "sew") (symbol_ref "INTVAL (operands[1])")) + (set (attr "vlmul") (symbol_ref "INTVAL (operands[2])")) + (set (attr "ta") (symbol_ref "INTVAL (operands[3])")) + (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))]) ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects. ;; Since we have many optmization passes from "expand" to "reload_completed",