From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 38F683858C31; Fri, 27 Jan 2023 09:59:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 38F683858C31 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1674813570; bh=O6XaV8NmIvN8WgoMHIsf7bRWltl8M8oMxo0xpTpGA/0=; h=From:To:Subject:Date:From; b=KfXra6eQeQv6tbTxnf4c465LpFNjr803yTyPceZ+OQDnk4PWtBnmmunq6pQ3lRfu3 K1Zf0gn3k0qhnTOnC5+Wyj44bF9fsIGXksqIAchLQBY72pDlJSV4oJhZyc/maX4Vqn mESgc2GCteSM4IyYggbGml+DtqKrMuMwFOoGkgv0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5432] RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: b0241ce6e37031e1cbde73d5389ec7f1d063e099 X-Git-Newrev: 0f024ff988aeaacd8d0f967c5f841ab20fb40c19 Message-Id: <20230127095930.38F683858C31@sourceware.org> Date: Fri, 27 Jan 2023 09:59:30 +0000 (GMT) List-Id: https://gcc.gnu.org/g:0f024ff988aeaacd8d0f967c5f841ab20fb40c19 commit r13-5432-g0f024ff988aeaacd8d0f967c5f841ab20fb40c19 Author: Ju-Zhe Zhong Date: Fri Jan 20 17:33:09 2023 +0800 RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x and zve32f. So it makes sense add predicate in the iterators of EEW = 64 vector modes. gcc/ChangeLog: * config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates. Diff: --- gcc/config/riscv/vector-iterators.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 840cd8d598a..c1ec23452bc 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -22,7 +22,8 @@ VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32") VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") VNx1SI VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") - VNx1DI VNx2DI VNx4DI (VNx8DI "TARGET_MIN_VLEN > 32") + (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32") + (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32") (VNx1SF "TARGET_VECTOR_ELEN_FP_32") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -38,7 +39,8 @@ (VNx4QI "TARGET_MIN_VLEN == 32") VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32") (VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") - VNx1DI VNx2DI VNx4DI (VNx8DI "TARGET_MIN_VLEN > 32") + (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32") + (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 32") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32")