From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 635073858D20; Sat, 28 Jan 2023 00:31:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 635073858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1674865885; bh=awS/7HhCAxH21864trpvo9GAfU27IpJxg8oWL2kT0C0=; h=From:To:Subject:Date:From; b=A5KMJfCRXOihX3CvyHdEt97m8QiY24KRS+FzcQjxhCM7ypQj18s4pz+7icrBU3KGE Wv+GzhN6wOkiL04e+nKZiytEDS5EN+ZAwm5WOSsWMl7PknbqPxdpG6tnvwM85q4G0p yBIwIK3w+yLBLr/IlbGM3KLXtU6amjhB2BUuPBk4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf007)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf007 X-Git-Oldrev: 3776ee48253214e069cdb0d51c20dd270bd24bd5 X-Git-Newrev: 95ed49fa47e084cc6b44436e10355eecc5756b43 Message-Id: <20230128003125.635073858D20@sourceware.org> Date: Sat, 28 Jan 2023 00:31:25 +0000 (GMT) List-Id: https://gcc.gnu.org/g:95ed49fa47e084cc6b44436e10355eecc5756b43 commit 95ed49fa47e084cc6b44436e10355eecc5756b43 Author: Michael Meissner Date: Fri Jan 27 19:31:21 2023 -0500 Revert patches Diff: --- gcc/config/rs6000/power10.md | 142 ++++++++++++++++++------------------ gcc/config/rs6000/rs6000-c.cc | 2 - gcc/config/rs6000/rs6000-cpus.def | 6 -- gcc/config/rs6000/rs6000-opts.h | 4 +- gcc/config/rs6000/rs6000-tables.opt | 3 - gcc/config/rs6000/rs6000.cc | 51 ++----------- gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 4 - gcc/doc/invoke.texi | 2 +- 10 files changed, 80 insertions(+), 137 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index caed2d53668..8e1d4e1afc6 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,STU_power10") ; stxvp (define_insn_reservation "power10-vecstore-pair" 0 (and (eq_attr "type" "vecstore") (eq_attr "size" "256") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,stu0_power10+stu1_power10") (define_insn_reservation "power10-larx" 4 (and (eq_attr "type" "load_l") (eq_attr "size" "!128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,LU_power10") ; All load quad forms (define_insn_reservation "power10-lq" 4 (and (eq_attr "type" "load,load_l") (eq_attr "size" "128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-stcx" 0 (and (eq_attr "type" "store_c") (eq_attr "size" "!128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,STU_power10") ; All store quad forms (define_insn_reservation "power10-stq" 0 (and (eq_attr "type" "store,store_c") (eq_attr "size" "128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,stu0_power10+stu1_power10") (define_insn_reservation "power10-sync" 1 (and (eq_attr "type" "sync,isync") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,STU_power10") @@ -248,7 +248,7 @@ (define_insn_reservation "power10-alu" 2 (and (eq_attr "type" "add,exts,integer,logical,isel") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") ; 4 cycle CR latency (define_bypass 4 "power10-alu" @@ -256,28 +256,28 @@ (define_insn_reservation "power10-fused_alu" 2 (and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") ; paddi (define_insn_reservation "power10-paddi" 2 (and (eq_attr "type" "add") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") ; Rotate/shift (non-record form) (define_insn_reservation "power10-rot" 2 (and (eq_attr "type" "insert,shift") (eq_attr "dot" "no") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") ; Record form rotate/shift (define_insn_reservation "power10-rot-compare" 3 (and (eq_attr "type" "insert,shift") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") ; 5 cycle CR latency (define_bypass 5 "power10-rot-compare" @@ -285,7 +285,7 @@ (define_insn_reservation "power10-alu2" 3 (and (eq_attr "type" "cntlz,popcnt,trap") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") ; 5 cycle CR latency (define_bypass 5 "power10-alu2" @@ -293,24 +293,24 @@ (define_insn_reservation "power10-cmp" 2 (and (eq_attr "type" "cmp") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") ; Treat 'two' and 'three' types as 2 or 3 way cracked (define_insn_reservation "power10-two" 4 (and (eq_attr "type" "two") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-three" 6 (and (eq_attr "type" "three") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_all_power10,EXU_power10") (define_insn_reservation "power10-mul" 5 (and (eq_attr "type" "mul") (eq_attr "dot" "no") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") ; 4 cycle MUL->MUL latency (define_bypass 4 "power10-mul" @@ -319,7 +319,7 @@ (define_insn_reservation "power10-mul-compare" 5 (and (eq_attr "type" "mul") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") ; 4 cycle MUL->MUL latency (define_bypass 4 "power10-mul-compare" @@ -331,13 +331,13 @@ (define_insn_reservation "power10-div" 12 (and (eq_attr "type" "div") (eq_attr "dot" "no") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-div-compare" 12 (and (eq_attr "type" "div") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") ; 14 cycle CR latency (define_bypass 14 "power10-div-compare" @@ -345,34 +345,34 @@ (define_insn_reservation "power10-crlogical" 2 (and (eq_attr "type" "cr_logical") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfcrf" 2 (and (eq_attr "type" "mfcrf") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfcr" 3 (and (eq_attr "type" "mfcr") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") ; Should differentiate between 1 cr field and > 1 since target of > 1 cr ; is cracked (define_insn_reservation "power10-mtcr" 3 (and (eq_attr "type" "mtcr") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mtjmpr" 3 (and (eq_attr "type" "mtjmpr") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfjmpr" 2 (and (eq_attr "type" "mfjmpr") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") @@ -380,126 +380,126 @@ (define_insn_reservation "power10-fpsimple" 3 (and (eq_attr "type" "fpsimple") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-fp" 5 (and (eq_attr "type" "fp,dmul") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-fpcompare" 3 (and (eq_attr "type" "fpcompare") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-sdiv" 22 (and (eq_attr "type" "sdiv") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-ddiv" 27 (and (eq_attr "type" "ddiv") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-sqrt" 26 (and (eq_attr "type" "ssqrt") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-dsqrt" 36 (and (eq_attr "type" "dsqrt") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vec-2cyc" 2 (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-fused-vec" 2 (and (eq_attr "type" "fused_vector") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-veccmp" 3 (and (eq_attr "type" "veccmp") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecsimple" 2 (and (eq_attr "type" "vecsimple") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecnormal" 5 (and (eq_attr "type" "vecfloat,vecdouble") (eq_attr "size" "!128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-qp" 12 (and (eq_attr "type" "vecfloat,vecdouble") (eq_attr "size" "128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecperm" 3 (and (eq_attr "type" "vecperm") (eq_attr "prefixed" "no") (eq_attr "dot" "no") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecperm-compare" 3 (and (eq_attr "type" "vecperm") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-prefixed-vecperm" 3 (and (eq_attr "type" "vecperm") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-veccomplex" 6 (and (eq_attr "type" "veccomplex") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecfdiv" 24 (and (eq_attr "type" "vecfdiv") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecdiv" 27 (and (eq_attr "type" "vecdiv") (eq_attr "size" "!128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-qpdiv" 56 (and (eq_attr "type" "vecdiv") (eq_attr "size" "128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-qpmul" 24 (and (eq_attr "type" "qmul") (eq_attr "size" "128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mtvsr" 2 (and (eq_attr "type" "mtvsr") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfvsr" 2 (and (eq_attr "type" "mfvsr") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") @@ -507,26 +507,26 @@ ; Branch is 2 cycles, grouped with STU for issue (define_insn_reservation "power10-branch" 2 (and (eq_attr "type" "jmpreg,branch") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-branch" 3 (and (eq_attr "type" "fused_mtbc") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,STU_power10") ; Crypto (define_insn_reservation "power10-crypto" 4 (and (eq_attr "type" "crypto") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") ; HTM (define_insn_reservation "power10-htm" 2 (and (eq_attr "type" "htmsimple,htm") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") @@ -535,26 +535,26 @@ (define_insn_reservation "power10-dfp" 12 (and (eq_attr "type" "dfp") (eq_attr "size" "!128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-dfpq" 12 (and (eq_attr "type" "dfp") (eq_attr "size" "128") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_power10") ; MMA (define_insn_reservation "power10-mma" 9 (and (eq_attr "type" "mma") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_any_power10,EXU_super_power10") (define_insn_reservation "power10-prefixed-mma" 9 (and (eq_attr "type" "mma") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,future")) + (eq_attr "cpu" "power10")) "DU_even_power10,EXU_super_power10") ; 4 cycle MMA->MMA latency (define_bypass 4 "power10-mma,power10-prefixed-mma" diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 2803014f2b6..8555174d36e 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -447,8 +447,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); if ((flags & OPTION_MASK_POWER10) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); - if ((flags & OPTION_MASK_FUTURE) != 0) - rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index deb4ea1c980..4f350da378c 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -86,10 +86,6 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) -/* Flags for a potential future processor that may or may not be delivered. */ -#define ISA_FUTURE_MASKS (ISA_3_1_MASKS_SERVER \ - | OPTION_MASK_FUTURE) - /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_P9_MINMAX) @@ -136,7 +132,6 @@ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ | OPTION_MASK_P10_FUSION \ - | OPTION_MASK_FUTURE \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ @@ -268,4 +263,3 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index f56f01d6fa5..8040cfdc06e 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -67,9 +67,7 @@ enum processor_type PROCESSOR_MPCCORE, PROCESSOR_CELL, PROCESSOR_PPCA2, - PROCESSOR_TITAN, - - PROCESSOR_FUTURE + PROCESSOR_TITAN }; diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 3ff28e39f6c..b82f8205fa1 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -197,6 +197,3 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue Enum(rs6000_cpu_opt_value) String(rs64) Value(56) -EnumValue -Enum(rs6000_cpu_opt_value) String(future) Value(57) - diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index ed26e2755cc..7e76c37fdab 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1085,27 +1085,6 @@ struct processor_costs power10_cost = { COSTS_N_INSNS (2), /* SF->DF convert */ }; -/* Instruction costs on Future processors. At the moment, this is a copy of - the power10 costs, but it is expected to change over time.. */ -static const -struct processor_costs future_cost = { - COSTS_N_INSNS (2), /* mulsi */ - COSTS_N_INSNS (2), /* mulsi_const */ - COSTS_N_INSNS (2), /* mulsi_const9 */ - COSTS_N_INSNS (2), /* muldi */ - COSTS_N_INSNS (6), /* divsi */ - COSTS_N_INSNS (6), /* divdi */ - COSTS_N_INSNS (2), /* fp */ - COSTS_N_INSNS (2), /* dmul */ - COSTS_N_INSNS (11), /* sdiv */ - COSTS_N_INSNS (13), /* ddiv */ - 128, /* cache line size */ - 32, /* l1 cache */ - 512, /* l2 cache */ - 16, /* prefetch streams */ - COSTS_N_INSNS (2), /* SF->DF convert */ -}; - /* Instruction costs on POWER A2 processors. */ static const struct processor_costs ppca2_cost = { @@ -4451,7 +4430,6 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER8 && rs6000_tune != PROCESSOR_POWER9 && rs6000_tune != PROCESSOR_POWER10 - && rs6000_tune != PROCESSOR_FUTURE && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4466,7 +4444,6 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4769,10 +4746,6 @@ rs6000_option_override_internal (bool global_init_p) rs6000_cost = &power10_cost; break; - case PROCESSOR_FUTURE: - rs6000_cost = &future_cost; - break; - case PROCESSOR_PPCA2: rs6000_cost = &ppca2_cost; break; @@ -5929,8 +5902,6 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL); - if ((flags & (ISA_FUTURE_MASKS & ~ISA_3_1_MASKS_SERVER)) != 0) - return "future"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) return "power10"; if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) @@ -10142,7 +10113,6 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, case PROCESSOR_POWER8: case PROCESSOR_POWER9: case PROCESSOR_POWER10: - case PROCESSOR_FUTURE: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -17942,8 +17912,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_FUTURE) + || rs6000_tune == PROCESSOR_POWER10) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -17982,7 +17951,6 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -18557,7 +18525,6 @@ rs6000_issue_rate (void) case PROCESSOR_POWER9: return 6; case PROCESSOR_POWER10: - case PROCESSOR_FUTURE: return 8; default: return 1; @@ -19273,10 +19240,8 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, if (rs6000_tune == PROCESSOR_POWER6) load_store_pendulum = 0; - /* Do Power10 dependent reordering. For now, assume "future" has the same - dependent reordering as power10. */ - if ((rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_FUTURE) && last_scheduled_insn) + /* Do Power10 dependent reordering. */ + if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) power10_sched_reorder (ready, n_ready - 1); return rs6000_issue_rate (); @@ -19300,10 +19265,8 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, && recog_memoized (last_scheduled_insn) >= 0) return power9_sched_reorder2 (ready, *pn_ready - 1); - /* Do Power10 dependent reordering. For now, assume "future" has the same - dependent reordering as power10. */ - if ((rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_FUTURE) && last_scheduled_insn) + /* Do Power10 dependent reordering. */ + if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) return power10_sched_reorder (ready, *pn_ready - 1); return cached_can_issue_more; @@ -22518,8 +22481,7 @@ rs6000_register_move_cost (machine_mode mode, allocation a move within the same class might turn out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_FUTURE) + || rs6000_tune == PROCESSOR_POWER10) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); @@ -24177,7 +24139,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, { "power10", OPTION_MASK_POWER10, false, true }, - { "future", OPTION_MASK_FUTURE, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 44fa355a061..3503614efbd 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -163,7 +163,6 @@ mcpu=e5500: -me5500; \ mcpu=e6500: -me6500; \ mcpu=titan: -mtitan; \ - mcpu=future: -mfuture; \ !mcpu*: %{mpower9-vector: -mpower9; \ mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ mvsx: -mpower7; \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5f933bede93..4a7812fa592 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -350,7 +350,7 @@ ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, power4,power5,power6,power7,power8,power9,power10, - rs64a,mpccore,cell,ppca2,titan,future" + rs64a,mpccore,cell,ppca2,titan" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 04532a774b9..bde6d3ff664 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -620,10 +620,6 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. -mfuture -Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) -Generate (do not generate) future instructions. - ; Documented parameters -param=rs6000-vect-unroll-limit= diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 15260d67063..06d77983e30 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -29184,7 +29184,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, @samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64}, -@samp{powerpc64le}, @samp{rs64}, @samp{future}, and @samp{native}. +@samp{powerpc64le}, @samp{rs64}, and @samp{native}. @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either