From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 21A293894C12; Tue, 31 Jan 2023 16:49:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 21A293894C12 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1675183781; bh=o/hcDprweQ0alDJ0h/fFISbPOVMQ7xPKQQ29R8HQ9bo=; h=From:To:Subject:Date:From; b=cerchRExJ0xbhu0gxdbNqC8fpDfAvCWFbctbDPcXgq+A888IaVz6JNWmXoxq4HGBW NDCgP8YenMkASbjTvQl7J/dRAxi/FSBp29IWX82gJLyrL942HLP2z3Zmm/2zvbtwMK 0Qdc/WkHPJsI7yQGig2Ndh1TLb7dldGe/vwPJ/9M= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5596] RISC-V: Add binop constraint tests X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: c2674f5b913ddec9d0b94d555ffd326b7f113c8d X-Git-Newrev: e96482d84ec801c43e651547ef70dfc86f9cbb62 Message-Id: <20230131164941.21A293894C12@sourceware.org> Date: Tue, 31 Jan 2023 16:49:41 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e96482d84ec801c43e651547ef70dfc86f9cbb62 commit r13-5596-ge96482d84ec801c43e651547ef70dfc86f9cbb62 Author: Ju-Zhe Zhong Date: Tue Jan 31 20:39:33 2023 +0800 RISC-V: Add binop constraint tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vv_constraint-1.c: New test. Diff: --- .../riscv/rvv/base/binop_vv_constraint-1.c | 132 +++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c new file mode 100644 index 00000000000..3ab1ccee035 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,tu,ma +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tu (v3, v2, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,ta,ma +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_m (mask, v3, v3, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,tu,mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tumu (mask, v3, v2, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f4: +** vsetivli\tzero,4,e8,mf8,tu,ma +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vse8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f4 (void * in, void *out) +{ + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4); + vint8mf8_t v3 = __riscv_vadd_vv_i8mf8 (v2, v2, 4); + vint8mf8_t v4 = __riscv_vadd_vv_i8mf8_tu (v3, v2, v2, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f5: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,ta,ma +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f5 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4); + vint8mf8_t v3 = __riscv_vadd_vv_i8mf8 (v2, v2, 4); + vint8mf8_t v4 = __riscv_vadd_vv_i8mf8_m (mask, v3, v3, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f6: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,tu,mu +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f6 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4); + vint8mf8_t v3 = __riscv_vadd_vv_i8mf8 (v2, v2, 4); + vint8mf8_t v4 = __riscv_vadd_vv_i8mf8_tumu (mask, v3, v2, v2, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +}