From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id A6D9A3844078; Tue, 31 Jan 2023 16:50:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A6D9A3844078 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1675183801; bh=QejnVDwJZAuAgG3cSlwAV+9p/ElzdNWf2He5Gb259Lk=; h=From:To:Subject:Date:From; b=ZSTKW60+BDYMjTyB90hY+eANHpM6M9KbRl4MOsUUUAAUe2Q/1t4eW05NJvMievKGf 799Uska5tru7XSdCxw6+SY7dKoyyZCThtk3JXT62sUALQ3POxgrqorhCjf48AGxGbE v8YapmsEKJR6rSQdj0hIiT/G+UIsELw4O+ipyMEw= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5600] RISC-V: Add vsrl.vv C++ API tests X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 768a8952539ca7dfb6a61f17595fa9f6ea1f27b2 X-Git-Newrev: f4463ea86a4b9855d204b8e8e612567017f07228 Message-Id: <20230131165001.A6D9A3844078@sourceware.org> Date: Tue, 31 Jan 2023 16:50:01 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f4463ea86a4b9855d204b8e8e612567017f07228 commit r13-5600-gf4463ea86a4b9855d204b8e8e612567017f07228 Author: Ju-Zhe Zhong Date: Tue Jan 31 20:58:20 2023 +0800 RISC-V: Add vsrl.vv C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vsrl_vv-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv-3.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C: New test. Diff: --- .../g++.target/riscv/rvv/base/vsrl_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C | 160 +++++++++++ 15 files changed, 2862 insertions(+) diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-1.C new file mode 100644 index 00000000000..21b6f49eb75 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-1.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vsrl(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-2.C new file mode 100644 index 00000000000..ce57b6c9e1d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-2.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8mf8_t test___riscv_vsrl(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-3.C new file mode 100644 index 00000000000..c44b6f75e69 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-3.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8mf8_t test___riscv_vsrl(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-1.C new file mode 100644 index 00000000000..4ae0bfda046 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-2.C new file mode 100644 index 00000000000..6780575dee4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-3.C new file mode 100644 index 00000000000..8ba4c22d0a3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-1.C new file mode 100644 index 00000000000..553965f9bf5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-2.C new file mode 100644 index 00000000000..97a4acfd21d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-3.C new file mode 100644 index 00000000000..31c2f6f1530 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-1.C new file mode 100644 index 00000000000..71732133e59 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-2.C new file mode 100644 index 00000000000..bb9e446ee3b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-3.C new file mode 100644 index 00000000000..3fdb30cc992 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C new file mode 100644 index 00000000000..0a807bae510 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C new file mode 100644 index 00000000000..cfb42441c9b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C new file mode 100644 index 00000000000..a5333829151 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */