[gcc r13-5601] RISC-V: Add vsra.vv C++ API tests

[Kito Cheng <kito@gcc.gnu.org>]

https://gcc.gnu.org/g:38e152f84b0667410a298cd487c38b70f7443c01

commit r13-5601-g38e152f84b0667410a298cd487c38b70f7443c01
Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date:   Tue Jan 31 20:59:58 2023 +0800

    RISC-V: Add vsra.vv C++ API tests
    
    gcc/testsuite/ChangeLog:
    
            * g++.target/riscv/rvv/base/vsra_vv-1.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv-2.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv-3.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_mu-1.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_mu-2.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_mu-3.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_tu-1.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_tu-2.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_tu-3.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_tum-1.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_tum-2.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_tum-3.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_tumu-1.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_tumu-2.C: New test.
            * g++.target/riscv/rvv/base/vsra_vv_tumu-3.C: New test.

Diff:
---
 .../g++.target/riscv/rvv/base/vsra_vv-1.C          | 314 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv-2.C          | 314 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv-3.C          | 314 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_mu-1.C       | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_mu-2.C       | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_mu-3.C       | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_tu-1.C       | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_tu-2.C       | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_tu-3.C       | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_tum-1.C      | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_tum-2.C      | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_tum-3.C      | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_tumu-1.C     | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_tumu-2.C     | 160 +++++++++++
 .../g++.target/riscv/rvv/base/vsra_vv_tumu-3.C     | 160 +++++++++++
 15 files changed, 2862 insertions(+)

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-1.C
new file mode 100644
index 00000000000..f7f849c91ff
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra(vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra(vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra(vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra(vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra(vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra(vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra(vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra(vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra(vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra(vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra(vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra(vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra(vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra(vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra(vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra(vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra(vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,vl);
+}
+
+
+vint8mf8_t test___riscv_vsra(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra(vbool16_t mask,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra(vbool32_t mask,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra(vbool16_t mask,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra(vbool64_t mask,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra(vbool32_t mask,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra(vbool16_t mask,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-2.C
new file mode 100644
index 00000000000..8d9c78a580a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra(vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra(vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra(vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra(vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra(vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra(vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra(vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra(vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra(vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra(vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra(vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra(vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra(vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra(vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra(vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra(vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra(vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,31);
+}
+
+
+vint8mf8_t test___riscv_vsra(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra(vbool16_t mask,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra(vbool32_t mask,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra(vbool16_t mask,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra(vbool64_t mask,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra(vbool32_t mask,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra(vbool16_t mask,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-3.C
new file mode 100644
index 00000000000..139ca62938b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra(vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra(vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra(vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra(vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra(vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra(vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra(vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra(vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra(vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra(vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra(vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra(vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra(vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra(vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra(vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra(vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra(vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra(op1,shift,32);
+}
+
+
+vint8mf8_t test___riscv_vsra(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra(vbool16_t mask,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra(vbool32_t mask,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra(vbool16_t mask,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra(vbool64_t mask,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra(vbool32_t mask,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra(vbool16_t mask,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-1.C
new file mode 100644
index 00000000000..1a0c5d52739
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-2.C
new file mode 100644
index 00000000000..7f84a65143e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-3.C
new file mode 100644
index 00000000000..23b89655cb1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-1.C
new file mode 100644
index 00000000000..26fa2dd96c4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-2.C
new file mode 100644
index 00000000000..facc6a5ea14
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-3.C
new file mode 100644
index 00000000000..82cc373d2b5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-1.C
new file mode 100644
index 00000000000..103d8b2e2d1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-2.C
new file mode 100644
index 00000000000..63d9a9a3d8c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-3.C
new file mode 100644
index 00000000000..4cd7296299f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-1.C
new file mode 100644
index 00000000000..a4a5f9918c4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-2.C
new file mode 100644
index 00000000000..f251b8952a1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-3.C
new file mode 100644
index 00000000000..920da123046
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */