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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf007)] Update lxvrl test for 32-bit. Date: Thu, 2 Feb 2023 02:58:32 +0000 (GMT) [thread overview] Message-ID: <20230202025832.72F713858D3C@sourceware.org> (raw) https://gcc.gnu.org/g:0c6bff190a28a2eed76da56d68e99a32565599ce commit 0c6bff190a28a2eed76da56d68e99a32565599ce Author: Michael Meissner <meissner@linux.ibm.com> Date: Wed Feb 1 21:58:09 2023 -0500 Update lxvrl test for 32-bit. 2023-02-01 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/rs6000-string.c (expand_block_move): Only generate LXVL and STXVL moves on 64-bit, since the pattern is not enabled on 32-bit. gcc/testsuite/ * gcc.target/powerpc/lxvrl.c: Restrict test to 64-bit. Diff: --- gcc/config/rs6000/rs6000-string.cc | 1 + gcc/testsuite/gcc.target/powerpc/lxvrl.c | 1 + 2 files changed, 2 insertions(+) diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 75e6f8803a5..9b2f1b83b22 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -2811,6 +2811,7 @@ expand_block_move (rtx operands[], bool might_overlap) gen_func.mov = gen_vsx_movv2di_64bit; } else if (TARGET_BLOCK_OPS_UNALIGNED_VSX + && TARGET_POWERPC64 && TARGET_POWER10 && bytes < 16 && orig_bytes > 16 && !(bytes == 1 || bytes == 2 diff --git a/gcc/testsuite/gcc.target/powerpc/lxvrl.c b/gcc/testsuite/gcc.target/powerpc/lxvrl.c index 83277dce6e4..71854c50c91 100644 --- a/gcc/testsuite/gcc.target/powerpc/lxvrl.c +++ b/gcc/testsuite/gcc.target/powerpc/lxvrl.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_future_ok } */ +/* { dg-require-effective-target lp64 } */ /* { dg-options "-mdejagnu-cpu=future -O2" } */ /* Test whether the lxvrl and stxvrl instructions are generated for
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