[gcc r13-5647] arm: Remove unnecessary zero-extending of MVE predicates before use [PR 107674]

[Andre Simoes Dias Vieira <avieira@gcc.gnu.org>]

https://gcc.gnu.org/g:d45ec8a732f449647afa89e46b80a4e0614ec28d

commit r13-5647-gd45ec8a732f449647afa89e46b80a4e0614ec28d
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Feb 2 10:01:13 2023 +0000

    arm: Remove unnecessary zero-extending of MVE predicates before use [PR 107674]
    
    This patch teaches GCC that zero-extending a MVE predicate from 16-bits to
    32-bits and then only using 16-bits is a no-op.
    It does so in two steps:
    - it lets gcc know that it can access any MVE predicate mode using any other MVE
    predicate mode without needing to copy it, using the TARGET_MODES_TIEABLE_P hook,
    - it teaches simplify_subreg to optimize a subreg with a vector outermode, by
    replacing this outermode with a same-sized integer mode and trying the
    avalailable optimizations, then if successful it surrounds the result with a
    subreg casting it back to the original vector outermode.
    
    gcc/ChangeLog:
    
            PR target/107674
            * config/arm/arm.cc (arm_hard_regno_mode_ok): Use new MACRO.
            (arm_modes_tieable_p): Make MVE predicate modes tieable.
            * config/arm/arm.h (VALID_MVE_PRED_MODE):  New define.
            * simplify-rtx.cc (simplify_context::simplify_subreg): Teach
            simplify_subreg to simplify subregs where the outermode is not scalar.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/mve_vpt.c: Change to remove unecessary zero-extend.

Diff:
---
 gcc/config/arm/arm.cc                      |  9 +++++----
 gcc/config/arm/arm.h                       |  4 ++++
 gcc/simplify-rtx.cc                        | 16 ++++++++++++++++
 gcc/testsuite/gcc.target/arm/mve/mve_vpt.c |  5 +----
 4 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index efc48349dd3..4d9d202cad1 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -25656,10 +25656,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
     return false;
 
   if (IS_VPR_REGNUM (regno))
-    return mode == HImode
-      || mode == V16BImode
-      || mode == V8BImode
-      || mode == V4BImode;
+    return VALID_MVE_PRED_MODE (mode);
 
   if (TARGET_THUMB1)
     /* For the Thumb we only allow values bigger than SImode in
@@ -25738,6 +25735,10 @@ arm_modes_tieable_p (machine_mode mode1, machine_mode mode2)
   if (GET_MODE_CLASS (mode1) == GET_MODE_CLASS (mode2))
     return true;
 
+  if (TARGET_HAVE_MVE
+      && (VALID_MVE_PRED_MODE (mode1) && VALID_MVE_PRED_MODE (mode2)))
+    return true;
+
   /* We specifically want to allow elements of "structure" modes to
      be tieable to the structure.  This more general condition allows
      other rarer situations too.  */
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 632728371d5..8325e7a876e 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1104,6 +1104,10 @@ extern const int arm_arch_cde_coproc_bits[];
    || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \
    || (MODE) == V2DFmode)
 
+#define VALID_MVE_PRED_MODE(MODE) \
+  ((MODE) == HImode							\
+   || (MODE) == V16BImode || (MODE) == V8BImode || (MODE) == V4BImode)
+
 #define VALID_MVE_SI_MODE(MODE) \
   ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \
    || (MODE) == V16QImode)
diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index 7fb1e97fbea..0a1dd88b0a8 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -7652,6 +7652,22 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
 	}
     }
 
+  /* Try simplifying a SUBREG expression of a non-integer OUTERMODE by using a
+     NEW_OUTERMODE of the same size instead, other simplifications rely on
+     integer to integer subregs and we'd potentially miss out on optimizations
+     otherwise.  */
+  if (known_gt (GET_MODE_SIZE (innermode),
+		GET_MODE_SIZE (outermode))
+      && SCALAR_INT_MODE_P (innermode)
+      && !SCALAR_INT_MODE_P (outermode)
+      && int_mode_for_size (GET_MODE_BITSIZE (outermode),
+			    0).exists (&int_outermode))
+    {
+      rtx tem = simplify_subreg (int_outermode, op, innermode, byte);
+      if (tem)
+	return simplify_gen_subreg (outermode, tem, GET_MODE (tem), 0);
+    }
+
   /* If OP is a vector comparison and the subreg is not changing the
      number of elements or the size of the elements, change the result
      of the comparison to the new mode.  */
diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_vpt.c b/gcc/testsuite/gcc.target/arm/mve/mve_vpt.c
index 28e4697c3c5..41f4e3805d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/mve_vpt.c
+++ b/gcc/testsuite/gcc.target/arm/mve/mve_vpt.c
@@ -16,12 +16,9 @@ void test0 (uint8_t *a, uint8_t *b, uint8_t *c)
 **	vldrb.8	q[0-9]+, \[r[0-9]+\]
 **	vldrb.8	q[0-9]+, \[r[0-9]+\]
 **	vcmp.i8	eq, q[0-9]+, q[0-9]+
-**	vmrs	(r[0-9]+), p0	@ movhi
-**	uxth	\1, \1
-**	vmsr	p0, \1	@ movhi
 **	vpst
 **	vaddt.i8	(q[0-9]+), q[0-9]+, q[0-9]+
 **	vpst
-**	vstrbt.8	\2, \[r[0-9]+\]
+**	vstrbt.8	\1, \[r[0-9]+\]
 **	bx	lr
 */