From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id E54AA3858C52; Thu, 2 Feb 2023 20:05:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E54AA3858C52 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1675368328; bh=RITGsUnO13kebqGc/Uu/7kYCu7luz2mpUGO/+WkR/7k=; h=From:To:Subject:Date:From; b=vDmN3zgs4pzUeVNd1EW1TPDhUu5zxnmUfbkAwz7woInvMJu405oicNKSyn60pslFO Sz9tOnFiKQKD1hAZVQi10fROE3CLlNzTP5sY1BplgB8mR8Tvc9VyObd03AfuZdLqQI OhXLioprFkL4fBAhJqvgkP/G5PG+fl6lzg5bQ9Fw= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf008)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf008 X-Git-Oldrev: 22a5fab72d4a9f2e43883a88080f4e74431815a7 X-Git-Newrev: 254c9b4bb2e58c4c05ac8fdbaf80d9f794aad6e1 Message-Id: <20230202200528.E54AA3858C52@sourceware.org> Date: Thu, 2 Feb 2023 20:05:28 +0000 (GMT) List-Id: https://gcc.gnu.org/g:254c9b4bb2e58c4c05ac8fdbaf80d9f794aad6e1 commit 254c9b4bb2e58c4c05ac8fdbaf80d9f794aad6e1 Author: Michael Meissner Date: Thu Feb 2 15:05:25 2023 -0500 Revert patches Diff: --- gcc/config/rs6000/mma.md | 345 +++++++--------------- gcc/config/rs6000/rs6000-c.cc | 3 - gcc/config/rs6000/rs6000.cc | 35 +-- gcc/testsuite/gcc.target/powerpc/dm-double-test.c | 194 ------------ gcc/testsuite/lib/target-supports.exp | 19 -- 5 files changed, 121 insertions(+), 475 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 411e2345291..59ca6835f7c 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -227,22 +227,13 @@ (define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")]) -(define_int_attr vvi4i4i8_dm [(UNSPEC_MMA_PMXVI4GER8 "pmdmxvi4ger8")]) - (define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "pmxvi4ger8pp")]) -(define_int_attr avvi4i4i8_dm [(UNSPEC_MMA_PMXVI4GER8PP "pmdmxvi4ger8pp")]) - (define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2 "pmxvi16ger2") (UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s") (UNSPEC_MMA_PMXVF16GER2 "pmxvf16ger2") (UNSPEC_MMA_PMXVBF16GER2 "pmxvbf16ger2")]) -(define_int_attr vvi4i4i2_dm [(UNSPEC_MMA_PMXVI16GER2 "pmdmxvi16ger2") - (UNSPEC_MMA_PMXVI16GER2S "pmdmxvi16ger2s") - (UNSPEC_MMA_PMXVF16GER2 "pmdmxvf16ger2") - (UNSPEC_MMA_PMXVBF16GER2 "pmdmxvbf16ger2")]) - (define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "pmxvi16ger2pp") (UNSPEC_MMA_PMXVI16GER2SPP "pmxvi16ger2spp") (UNSPEC_MMA_PMXVF16GER2PP "pmxvf16ger2pp") @@ -254,54 +245,25 @@ (UNSPEC_MMA_PMXVBF16GER2NP "pmxvbf16ger2np") (UNSPEC_MMA_PMXVBF16GER2NN "pmxvbf16ger2nn")]) -(define_int_attr avvi4i4i2_dm [(UNSPEC_MMA_PMXVI16GER2PP "pmdmxvi16ger2pp") - (UNSPEC_MMA_PMXVI16GER2SPP "pmdmxvi16ger2spp") - (UNSPEC_MMA_PMXVF16GER2PP "pmdmxvf16ger2pp") - (UNSPEC_MMA_PMXVF16GER2PN "pmdmxvf16ger2pn") - (UNSPEC_MMA_PMXVF16GER2NP "pmdmxvf16ger2np") - (UNSPEC_MMA_PMXVF16GER2NN "pmdmxvf16ger2nn") - (UNSPEC_MMA_PMXVBF16GER2PP "pmdmxvbf16ger2pp") - (UNSPEC_MMA_PMXVBF16GER2PN "pmdmxvbf16ger2pn") - (UNSPEC_MMA_PMXVBF16GER2NP "pmdmxvbf16ger2np") - (UNSPEC_MMA_PMXVBF16GER2NN "pmdmxvbf16ger2nn")]) - (define_int_attr vvi4i4 [(UNSPEC_MMA_PMXVF32GER "pmxvf32ger")]) -(define_int_attr vvi4i4_dm [(UNSPEC_MMA_PMXVF32GER "pmdmxvf32ger")]) - (define_int_attr avvi4i4 [(UNSPEC_MMA_PMXVF32GERPP "pmxvf32gerpp") (UNSPEC_MMA_PMXVF32GERPN "pmxvf32gerpn") (UNSPEC_MMA_PMXVF32GERNP "pmxvf32gernp") (UNSPEC_MMA_PMXVF32GERNN "pmxvf32gernn")]) -(define_int_attr avvi4i4_dm [(UNSPEC_MMA_PMXVF32GERPP "pmdmxvf32gerpp") - (UNSPEC_MMA_PMXVF32GERPN "pmdmxvf32gerpn") - (UNSPEC_MMA_PMXVF32GERNP "pmdmxvf32gernp") - (UNSPEC_MMA_PMXVF32GERNN "pmdmxvf32gernn")]) - (define_int_attr pvi4i2 [(UNSPEC_MMA_PMXVF64GER "pmxvf64ger")]) -(define_int_attr pvi4i2_dm [(UNSPEC_MMA_PMXVF64GER "pmdmxvf64ger")]) - (define_int_attr apvi4i2 [(UNSPEC_MMA_PMXVF64GERPP "pmxvf64gerpp") (UNSPEC_MMA_PMXVF64GERPN "pmxvf64gerpn") (UNSPEC_MMA_PMXVF64GERNP "pmxvf64gernp") (UNSPEC_MMA_PMXVF64GERNN "pmxvf64gernn")]) -(define_int_attr apvi4i2_dm [(UNSPEC_MMA_PMXVF64GERPP "pmdmxvf64gerpp") - (UNSPEC_MMA_PMXVF64GERPN "pmdmxvf64gerpn") - (UNSPEC_MMA_PMXVF64GERNP "pmdmxvf64gernp") - (UNSPEC_MMA_PMXVF64GERNN "pmdmxvf64gernn")]) - (define_int_attr vvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4 "pmxvi8ger4")]) -(define_int_attr vvi4i4i4_dm [(UNSPEC_MMA_PMXVI8GER4 "pmdmxvi8ger4")]) - (define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "pmxvi8ger4pp") (UNSPEC_MMA_PMXVI8GER4SPP "pmxvi8ger4spp")]) -(define_int_attr avvi4i4i4_dm [(UNSPEC_MMA_PMXVI8GER4PP "pmdmxvi8ger4pp") - (UNSPEC_MMA_PMXVI8GER4SPP "pmdmxvi8ger4spp")]) ;; Vector pair support. OOmode can only live in VSRs. (define_expand "movoo" @@ -590,285 +552,190 @@ "dmxxextfdmr256 %0,%1,2" [(set_attr "type" "mma")]) -;; MMA instructions that do not use their accumulators as an input, still must -;; not allow their vector operands to overlap the registers used by the -;; accumulator. We enforce this by marking the output as early clobber. If we -;; have dense math, we don't need the whole prime/de-prime action, so just make -;; thse instructions be NOPs. - -(define_expand "mma_" - [(set (match_operand:XO 0 "register_operand") - (unspec:XO [(match_operand:XO 1 "register_operand")] - MMA_ACC))] - "TARGET_MMA" -{ - if (TARGET_DENSE_MATH) - { - if (!rtx_equal_p (operands[0], operands[1])) - emit_move_insn (operands[0], operands[1]); - DONE; - } - - /* Generate the prime/de-prime code. */ -}) - -(define_insn "*mma_" +(define_insn "mma_" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")] MMA_ACC))] - "TARGET_MMA && !TARGET_DENSE_MATH" + "TARGET_MMA" " %A0" [(set_attr "type" "mma")]) ;; We can't have integer constants in XOmode so we wrap this in an -;; UNSPEC_VOLATILE for the non-dense math case. For dense math, we don't need -;; to disable optimization and we can do a normal UNSPEC. +;; UNSPEC_VOLATILE. -(define_expand "mma_xxsetaccz" - [(set (match_operand:XO 0 "register_operand") - (unspec_volatile:XO [(const_int 0)] - UNSPECV_MMA_XXSETACCZ))] - "TARGET_MMA" -{ - if (TARGET_DENSE_MATH) - { - emit_insn (gen_mma_xxsetaccz_dm (operands[0])); - DONE; - } -}) - -(define_insn "*mma_xxsetaccz_vsx" +(define_insn "mma_xxsetaccz" [(set (match_operand:XO 0 "fpr_reg_operand" "=d") (unspec_volatile:XO [(const_int 0)] UNSPECV_MMA_XXSETACCZ))] - "TARGET_MMA && !TARGET_DENSE_MATH" + "TARGET_MMA" "xxsetaccz %A0" [(set_attr "type" "mma")]) - -(define_insn "mma_xxsetaccz_dm" - [(set (match_operand:XO 0 "dmr_operand" "=wD") - (unspec:XO [(const_int 0)] - UNSPECV_MMA_XXSETACCZ))] - "TARGET_DENSE_MATH" - "dmsetdmrz %0" - [(set_attr "type" "mma")]) - (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")] MMA_VV))] "TARGET_MMA" - "@ - dm %A0,%x1,%x2 - %A0,%x1,%x2 - %A0,%x1,%x2" - [(set_attr "type" "mma") - (set_attr "isa" "dm,not_dm,not_dm")]) + " %A0,%x1,%x2" + [(set_attr "type" "mma")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")] MMA_AVV))] "TARGET_MMA" " %A0,%x2,%x3" - [(set_attr "type" "mma") - (set_attr "isa" "dm,not_dm,not_dm")]) + [(set_attr "type" "mma")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")] MMA_PV))] "TARGET_MMA" - "@ - dm %A0,%x1,%x2 - %A0,%x1,%x2 - %A0,%x1,%x2" - [(set_attr "type" "mma") - (set_attr "isa" "dm,not_dm,not_dm")]) + " %A0,%x1,%x2" + [(set_attr "type" "mma")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0") - (match_operand:OO 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + (match_operand:OO 2 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")] MMA_APV))] "TARGET_MMA" - "@ - dm %A0,%x2,%x3 - %A0,%x2,%x3 - %A0,%x2,%x3" - [(set_attr "type" "mma") - (set_attr "isa" "dm,not_dm,not_dm")]) + " %A0,%x2,%x3" + [(set_attr "type" "mma")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 3 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 4 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 5 "u8bit_cint_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:SI 3 "const_0_to_15_operand" "n,n") + (match_operand:SI 4 "const_0_to_15_operand" "n,n") + (match_operand:SI 5 "u8bit_cint_operand" "n,n")] MMA_VVI4I4I8))] "TARGET_MMA" - "@ - dm %A0,%x1,%x2,%3,%4,%5 - %A0,%x1,%x2,%3,%4,%5 - %A0,%x1,%x2,%3,%4,%5" + " %A0,%x1,%x2,%3,%4,%5" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 4 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 5 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 6 "u8bit_cint_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") + (match_operand:SI 4 "const_0_to_15_operand" "n,n") + (match_operand:SI 5 "const_0_to_15_operand" "n,n") + (match_operand:SI 6 "u8bit_cint_operand" "n,n")] MMA_AVVI4I4I8))] "TARGET_MMA" " %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 3 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 4 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 5 "const_0_to_3_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:SI 3 "const_0_to_15_operand" "n,n") + (match_operand:SI 4 "const_0_to_15_operand" "n,n") + (match_operand:SI 5 "const_0_to_3_operand" "n,n")] MMA_VVI4I4I2))] "TARGET_MMA" - "@ - %A0,%x1,%x2,%3,%4,%5 - %A0,%x1,%x2,%3,%4,%5 - %A0,%x1,%x2,%3,%4,%5" + " %A0,%x1,%x2,%3,%4,%5" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 4 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 5 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 6 "const_0_to_3_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") + (match_operand:SI 4 "const_0_to_15_operand" "n,n") + (match_operand:SI 5 "const_0_to_15_operand" "n,n") + (match_operand:SI 6 "const_0_to_3_operand" "n,n")] MMA_AVVI4I4I2))] "TARGET_MMA" - "@ - %A0,%x2,%x3,%4,%5,%6 - %A0,%x2,%x3,%4,%5,%6 - %A0,%x2,%x3,%4,%5,%6" + " %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 3 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:SI 3 "const_0_to_15_operand" "n,n") + (match_operand:SI 4 "const_0_to_15_operand" "n,n")] MMA_VVI4I4))] "TARGET_MMA" - "@ - %A0,%x1,%x2,%3,%4 - %A0,%x1,%x2,%3,%4 - %A0,%x1,%x2,%3,%4" + " %A0,%x1,%x2,%3,%4" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 4 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") + (match_operand:SI 4 "const_0_to_15_operand" "n,n") + (match_operand:SI 5 "const_0_to_15_operand" "n,n")] MMA_AVVI4I4))] "TARGET_MMA" - "@ - %A0,%x2,%x3,%4,%5 - %A0,%x2,%x3,%4,%5 - %A0,%x2,%x3,%4,%5" + " %A0,%x2,%x3,%4,%5" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 3 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 4 "const_0_to_3_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:SI 3 "const_0_to_15_operand" "n,n") + (match_operand:SI 4 "const_0_to_3_operand" "n,n")] MMA_PVI4I2))] "TARGET_MMA" - "@ - %A0,%x1,%x2,%3,%4 - %A0,%x1,%x2,%3,%4 - %A0,%x1,%x2,%3,%4" + " %A0,%x1,%x2,%3,%4" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0") - (match_operand:OO 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 4 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 5 "const_0_to_3_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + (match_operand:OO 2 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") + (match_operand:SI 4 "const_0_to_15_operand" "n,n") + (match_operand:SI 5 "const_0_to_3_operand" "n,n")] MMA_APVI4I2))] "TARGET_MMA" - "@ - %A0,%x2,%x3,%4,%5 - %A0,%x2,%x3,%4,%5 - %A0,%x2,%x3,%4,%5" + " %A0,%x2,%x3,%4,%5" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 3 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 4 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:SI 3 "const_0_to_15_operand" "n,n") + (match_operand:SI 4 "const_0_to_15_operand" "n,n") + (match_operand:SI 5 "const_0_to_15_operand" "n,n")] MMA_VVI4I4I4))] "TARGET_MMA" - "@ - %A0,%x1,%x2,%3,%4,%5 - %A0,%x1,%x2,%3,%4,%5 - %A0,%x1,%x2,%3,%4,%5" + " %A0,%x1,%x2,%3,%4,%5" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0") - (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa") - (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa") - (match_operand:SI 4 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 5 "const_0_to_15_operand" "n,n,n") - (match_operand:SI 6 "const_0_to_15_operand" "n,n,n")] + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") + (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") + (match_operand:SI 4 "const_0_to_15_operand" "n,n") + (match_operand:SI 5 "const_0_to_15_operand" "n,n") + (match_operand:SI 6 "const_0_to_15_operand" "n,n")] MMA_AVVI4I4I4))] "TARGET_MMA" - "@ - %A0,%x2,%x3,%4,%5,%6 - %A0,%x2,%x3,%4,%5,%6 - %A0,%x2,%x3,%4,%5,%6" + " %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") - (set_attr "prefixed" "yes") - (set_attr "isa" "dm,not_dm,not_dm")]) + (set_attr "prefixed" "yes")]) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index baf1f4dc92b..2803014f2b6 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -600,9 +600,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) /* Tell the user if we support the MMA instructions. */ if ((flags & OPTION_MASK_MMA) != 0) rs6000_define_or_undefine_macro (define_p, "__MMA__"); - /* Tell the user if we support the dense math instructions. */ - if ((flags & OPTION_MASK_DENSE_MATH) != 0) - rs6000_define_or_undefine_macro (define_p, "__PPC_DMR__"); /* Whether pc-relative code is being generated. */ if ((flags & OPTION_MASK_PCREL) != 0) rs6000_define_or_undefine_macro (define_p, "__PCREL__"); diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index c8f05f6f2d7..8ecb3021ff9 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -13910,13 +13910,8 @@ print_operand (FILE *file, rtx x, int code) overlapping with the FPR registers. */ if (!REG_P (x)) output_operand_lossage ("invalid %%A value"); - else if (TARGET_DENSE_MATH) - { - if (DMR_REGNO_P (REGNO (x))) - fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO); - else - output_operand_lossage ("%%A operand is not a DMR"); - } + else if (TARGET_DENSE_MATH && DMR_REGNO_P (REGNO (x))) + fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO); else if (!FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0) output_operand_lossage ("invalid %%A value"); else @@ -27361,7 +27356,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we are reading an accumulator register, we have to deprime it before we can access it. */ - if (TARGET_MMA && !TARGET_DENSE_MATH + if (TARGET_MMA && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src))) emit_insn (gen_mma_xxmfacc (src, src)); @@ -27393,9 +27388,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) emit_insn (gen_rtx_SET (dst2, src2)); } - /* If we are writing an accumulator register that overlaps with the - FPR registers, we have to prime it after we've written it. */ - if (TARGET_MMA && !TARGET_DENSE_MATH + /* If we are writing an accumulator register, we have to + prime it after we've written it. */ + if (TARGET_MMA && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst))) emit_insn (gen_mma_xxmtacc (dst, dst)); @@ -27464,9 +27459,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) emit_insn (gen_rtx_SET (dst_i, op)); } - /* On systems without dense math where accumulators overlap with the - vector registers, we have to prime it after we've written it. */ - if (GET_MODE (src) == XOmode && !TARGET_DENSE_MATH) + /* We are writing an accumulator register, so we have to + prime it after we've written it. */ + if (GET_MODE (src) == XOmode) emit_insn (gen_mma_xxmtacc (dst, dst)); return; @@ -27477,9 +27472,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) { - /* If we are reading an accumulator register and we don't have dense - math, we have to deprime it before we can access it. */ - if (TARGET_MMA && !TARGET_DENSE_MATH + /* If we are reading an accumulator register, we have to + deprime it before we can access it. */ + if (TARGET_MMA && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src))) emit_insn (gen_mma_xxmfacc (src, src)); @@ -27507,7 +27502,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we are writing an accumulator register, we have to prime it after we've written it. */ - if (TARGET_MMA && !TARGET_DENSE_MATH + if (TARGET_MMA && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst))) emit_insn (gen_mma_xxmtacc (dst, dst)); } @@ -27644,7 +27639,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we are reading an accumulator register, we have to deprime it before we can access it. */ - if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (src) + if (TARGET_MMA && REG_P (src) && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src))) emit_insn (gen_mma_xxmfacc (src, src)); @@ -27676,7 +27671,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we are writing an accumulator register, we have to prime it after we've written it. */ - if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (dst) + if (TARGET_MMA && REG_P (dst) && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst))) emit_insn (gen_mma_xxmtacc (dst, dst)); diff --git a/gcc/testsuite/gcc.target/powerpc/dm-double-test.c b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c deleted file mode 100644 index 66c19779585..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/dm-double-test.c +++ /dev/null @@ -1,194 +0,0 @@ -/* Test derived from mma-double-1.c, modified for dense math. */ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_dense_math_ok } */ -/* { dg-options "-mdejagnu-cpu=future -O2" } */ - -#include -#include -#include - -typedef unsigned char vec_t __attribute__ ((vector_size (16))); -typedef double v4sf_t __attribute__ ((vector_size (16))); -#define SAVE_ACC(ACC, ldc, J) \ - __builtin_mma_disassemble_acc (result, ACC); \ - rowC = (v4sf_t *) &CO[0*ldc+J]; \ - rowC[0] += result[0]; \ - rowC = (v4sf_t *) &CO[1*ldc+J]; \ - rowC[0] += result[1]; \ - rowC = (v4sf_t *) &CO[2*ldc+J]; \ - rowC[0] += result[2]; \ - rowC = (v4sf_t *) &CO[3*ldc+J]; \ - rowC[0] += result[3]; - -void -DM (int m, int n, int k, double *A, double *B, double *C) -{ - __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; - v4sf_t result[4]; - v4sf_t *rowC; - for (int l = 0; l < n; l += 4) - { - double *CO; - double *AO; - AO = A; - CO = C; - C += m * 4; - for (int j = 0; j < m; j += 16) - { - double *BO = B; - __builtin_mma_xxsetaccz (&acc0); - __builtin_mma_xxsetaccz (&acc1); - __builtin_mma_xxsetaccz (&acc2); - __builtin_mma_xxsetaccz (&acc3); - __builtin_mma_xxsetaccz (&acc4); - __builtin_mma_xxsetaccz (&acc5); - __builtin_mma_xxsetaccz (&acc6); - __builtin_mma_xxsetaccz (&acc7); - unsigned long i; - - for (i = 0; i < k; i++) - { - vec_t *rowA = (vec_t *) & AO[i * 16]; - __vector_pair rowB; - vec_t *rb = (vec_t *) & BO[i * 4]; - __builtin_mma_assemble_pair (&rowB, rb[1], rb[0]); - __builtin_mma_xvf64gerpp (&acc0, rowB, rowA[0]); - __builtin_mma_xvf64gerpp (&acc1, rowB, rowA[1]); - __builtin_mma_xvf64gerpp (&acc2, rowB, rowA[2]); - __builtin_mma_xvf64gerpp (&acc3, rowB, rowA[3]); - __builtin_mma_xvf64gerpp (&acc4, rowB, rowA[4]); - __builtin_mma_xvf64gerpp (&acc5, rowB, rowA[5]); - __builtin_mma_xvf64gerpp (&acc6, rowB, rowA[6]); - __builtin_mma_xvf64gerpp (&acc7, rowB, rowA[7]); - } - SAVE_ACC (&acc0, m, 0); - SAVE_ACC (&acc2, m, 4); - SAVE_ACC (&acc1, m, 2); - SAVE_ACC (&acc3, m, 6); - SAVE_ACC (&acc4, m, 8); - SAVE_ACC (&acc6, m, 12); - SAVE_ACC (&acc5, m, 10); - SAVE_ACC (&acc7, m, 14); - AO += k * 16; - BO += k * 4; - CO += 16; - } - B += k * 4; - } -} - -void -init (double *matrix, int row, int column) -{ - for (int j = 0; j < column; j++) - { - for (int i = 0; i < row; i++) - { - matrix[j * row + i] = (i * 16 + 2 + j) / 0.123; - } - } -} - -void -init0 (double *matrix, double *matrix1, int row, int column) -{ - for (int j = 0; j < column; j++) - for (int i = 0; i < row; i++) - matrix[j * row + i] = matrix1[j * row + i] = 0; -} - - -void -print (const char *name, const double *matrix, int row, int column) -{ - printf ("Matrix %s has %d rows and %d columns:\n", name, row, column); - for (int i = 0; i < row; i++) - { - for (int j = 0; j < column; j++) - { - printf ("%f ", matrix[j * row + i]); - } - printf ("\n"); - } - printf ("\n"); -} - -int -main (int argc, char *argv[]) -{ - int rowsA, colsB, common; - int i, j, k; - int ret = 0; - - for (int t = 16; t <= 128; t += 16) - { - for (int t1 = 4; t1 <= 16; t1 += 4) - { - rowsA = t; - colsB = t1; - common = 1; - /* printf ("Running test for rows = %d,cols = %d\n", t, t1); */ - double A[rowsA * common]; - double B[common * colsB]; - double C[rowsA * colsB]; - double D[rowsA * colsB]; - - - init (A, rowsA, common); - init (B, common, colsB); - init0 (C, D, rowsA, colsB); - DM (rowsA, colsB, common, A, B, C); - - for (i = 0; i < colsB; i++) - { - for (j = 0; j < rowsA; j++) - { - D[i * rowsA + j] = 0; - for (k = 0; k < common; k++) - { - D[i * rowsA + j] += - A[k * rowsA + j] * B[k + common * i]; - } - } - } - for (i = 0; i < colsB; i++) - { - for (j = 0; j < rowsA; j++) - { - for (k = 0; k < common; k++) - { - if (D[i * rowsA + j] != C[i * rowsA + j]) - { - printf ("Error %d,%d,%d\n",i,j,k); - ret++; - } - } - } - } - if (ret) - { - print ("A", A, rowsA, common); - print ("B", B, common, colsB); - print ("C", C, rowsA, colsB); - print ("D", D, rowsA, colsB); - } - } - } - -#ifdef VERBOSE - if (ret) - printf ("DM double test fail: %d errors\n",ret); - else - printf ("DM double test success: 0 DM errors\n"); -#else - if (ret) - abort(); -#endif - - return ret; -} - -/* { dg-final { scan-assembler {\mdmsetdmrz\M} } } */ -/* { dg-final { scan-assembler {\mdmxvf64gerpp\M} } } */ -/* { dg-final { scan-assembler {\mdmxxextfdmr512\M} } } */ - diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 9586ed3ae47..227e3004077 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6581,25 +6581,6 @@ proc check_effective_target_power10_ok { } { } } -# Return 1 if this is a PowerPC target supporting -mcpu=future or -mdense-math -# which enables the dense math operations. -proc check_effective_target_powerpc_dense_math_ok { } { - return [check_no_compiler_messages_nocache powerpc_dense_math_ok assembly { - __vector_quad vq; - void test (void) - { - #ifndef __PPC_DMR__ - #error "target does not have dense math support." - #else - /* Make sure we have dense math support. */ - __vector_quad dmr; - __asm__ ("dmsetaccz %A0" : "=wD" (dmr)); - vq = dmr; - #endif - } - } "-mcpu=future"] -} - # Return 1 if this is a PowerPC target supporting -mfloat128 via either # software emulation on power7/power8 systems or hardware support on power9.