From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id E54B33858031; Fri, 3 Feb 2023 07:15:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E54B33858031 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1675408524; bh=bYBFWjI9PK7gfOfjn1WUaZ1INf87fX3ujs2Ql033/20=; h=From:To:Subject:Date:From; b=rWr6TwRMRuN7Bxb8Dii8D34uaUYsnhpw4ywDy5efo6HzZO0QQf6mkEz8gPmC4ZCEc Tb0a+vXjsLIZO3qCO8u3WTDaAMKene7+Z6piO81Am487mSrfS6MihMvJ3LN4KhX/PB kfH7vtqSq/ld04BproP4UOel6H2WUm/SmF0eHVSI= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5673] RISC-V: Add shift constraint tests X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 07fba8d6f2da481c8d2915e66d49525c65ca04d6 X-Git-Newrev: 6c93c1fb3969648cb9b4e330c796d6520aa0c9e8 Message-Id: <20230203071524.E54B33858031@sourceware.org> Date: Fri, 3 Feb 2023 07:15:24 +0000 (GMT) List-Id: https://gcc.gnu.org/g:6c93c1fb3969648cb9b4e330c796d6520aa0c9e8 commit r13-5673-g6c93c1fb3969648cb9b4e330c796d6520aa0c9e8 Author: Ju-Zhe Zhong Date: Wed Feb 1 06:15:13 2023 +0800 RISC-V: Add shift constraint tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: New test. Diff: --- .../riscv/rvv/base/shift_vx_constraint-1.c | 133 +++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c new file mode 100644 index 00000000000..ae3883c5af9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c @@ -0,0 +1,133 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,tu,ma +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,31 +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,31 +** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 31, 4); + vint32m1_t v4 = __riscv_vsll_vx_i32m1_tu (v3, v2, 31, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** vsetivli\tzero,4,e32,m1,ta,ma +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 32, 4); + vint32m1_t v4 = __riscv_vsll_vx_i32m1_m (mask, v3, 32, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,tu,mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17 +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 17, 4); + vint32m1_t v4 = __riscv_vsll_vx_i32m1_tumu (mask, v3, v2, 17, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f4: +** vsetivli\tzero,4,e8,mf8,tu,ma +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vse8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f4 (void * in, void *out, size_t x) +{ + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4); + vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4); + vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tu (v3, v2, x, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f5: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,ta,ma +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5 +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f5 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4); + vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, 5, 4); + vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_m (mask, v3, 5, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f6: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,tu,mu +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f6 (void * in, void *out, size_t x) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4); + vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4); + vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tumu (mask, v3, v2, x, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +}