From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 89A733857352; Fri, 3 Feb 2023 07:15:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 89A733857352 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1675408550; bh=R6WFsGSUf77m0px6dyk0PIJOjaiaTW8f2ahyYh/i7S4=; h=From:To:Subject:Date:From; b=RMVn++nRr/J0jRkCjV+kEdHTAw1P4FA372SQ2w3D6SK5nzyC5H+oTwAFYGtP2CsuR 6Z4a7PyH3bL1XBjuoVQib85/mtQPALLUbCGV0ff8jv++tPd83kyOA/TW5JBSCvjOYF DifqpRELnwhp/vVuQuzxq89kFbK6DYMlo1+MkX6k= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5678] RISC-V: Remove unnecessary register class. X-Act-Checkin: gcc X-Git-Author: Monk Chiang X-Git-Refname: refs/heads/master X-Git-Oldrev: f3a10f4fff3d6751aa65df58b8629f84a0c04545 X-Git-Newrev: 167b04b9b8a2becfd23b8ccf7f09016bbd013e12 Message-Id: <20230203071550.89A733857352@sourceware.org> Date: Fri, 3 Feb 2023 07:15:50 +0000 (GMT) List-Id: https://gcc.gnu.org/g:167b04b9b8a2becfd23b8ccf7f09016bbd013e12 commit r13-5678-g167b04b9b8a2becfd23b8ccf7f09016bbd013e12 Author: Monk Chiang Date: Fri Feb 3 12:58:51 2023 +0800 RISC-V: Remove unnecessary register class. Avoid VL_REGS, VTYPE_REGS join register allocation. gcc/ChangeLog: * config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class. * config/riscv/riscv.cc: Ditto. Diff: --- gcc/config/riscv/riscv.cc | 8 +------- gcc/config/riscv/riscv.h | 8 +------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 209d9a53e7b..3b7804b7501 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -293,7 +293,7 @@ const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, - FRAME_REGS, FRAME_REGS, VL_REGS, VTYPE_REGS, + FRAME_REGS, FRAME_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, @@ -5831,12 +5831,6 @@ riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) if (reg_class_subset_p (rclass, V_REGS)) return riscv_hard_regno_nregs (V_REG_FIRST, mode); - if (reg_class_subset_p (rclass, VL_REGS)) - return 1; - - if (reg_class_subset_p (rclass, VTYPE_REGS)) - return 1; - return 0; } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 0ab739bd6eb..faffd5a77fe 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -462,8 +462,6 @@ enum reg_class GR_REGS, /* integer registers */ FP_REGS, /* floating-point registers */ FRAME_REGS, /* arg pointer and frame pointer */ - VL_REGS, /* vl register */ - VTYPE_REGS, /* vtype register */ VM_REGS, /* v0.t registers */ VD_REGS, /* vector registers except v0.t */ V_REGS, /* vector registers */ @@ -487,8 +485,6 @@ enum reg_class "GR_REGS", \ "FP_REGS", \ "FRAME_REGS", \ - "VL_REGS", \ - "VTYPE_REGS", \ "VM_REGS", \ "VD_REGS", \ "V_REGS", \ @@ -514,12 +510,10 @@ enum reg_class { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FP_REGS */ \ { 0x00000000, 0x00000000, 0x00000003, 0x00000000 }, /* FRAME_REGS */ \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* VL_REGS */ \ - { 0x00000000, 0x00000000, 0x00000008, 0x00000000 }, /* VTYPE_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe }, /* VNoV0_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* V_REGS */ \ - { 0xffffffff, 0xffffffff, 0x0000000f, 0xffffffff } /* ALL_REGS */ \ + { 0xffffffff, 0xffffffff, 0x00000003, 0xffffffff } /* ALL_REGS */ \ } /* A C expression whose value is a register class containing hard