[gcc(refs/users/meissner/heads/dmf008)] Revert patches

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:e625820b066fc5631c38bf0b83e5e905496e2931

commit e625820b066fc5631c38bf0b83e5e905496e2931
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Feb 3 14:25:11 2023 -0500

    Revert patches

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc         |  17 ----
 gcc/config/rs6000/rs6000-builtins.def       |  11 ---
 gcc/config/rs6000/rs6000-gen-builtins.cc    |  35 ++------
 gcc/config/rs6000/rs6000-string.cc          |   1 -
 gcc/config/rs6000/rs6000.md                 |  60 --------------
 gcc/config/rs6000/vsx.md                    | 122 +++++-----------------------
 gcc/doc/extend.texi                         |  24 ------
 gcc/testsuite/gcc.target/powerpc/lxvrl.c    |  32 --------
 gcc/testsuite/gcc.target/powerpc/subfus-1.c |  32 --------
 gcc/testsuite/gcc.target/powerpc/subfus-2.c |  32 --------
 gcc/testsuite/lib/target-supports.exp       |  16 +---
 11 files changed, 28 insertions(+), 354 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index b9b0b2d52d0..d971cf90e51 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -139,17 +139,6 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode)
     case ENB_MMA:
       error ("%qs requires the %qs option", name, "-mmma");
       break;
-    case ENB_FUTURE:
-      error ("%qs requires the %qs option", name, "-mcpu=future");
-      break;
-    case ENB_FUTURE_64:
-      error ("%qs requires the %qs option and either the %qs or %qs option",
-	     name, "-mcpu=future", "-m64", "-mpowerpc64");
-      break;
-    case ENB_DM:
-      error ("%qs requires the %qs or %qs options", name, "-mcpu=future",
-	     "-mdense-math");
-      break;
     default:
     case ENB_ALWAYS:
       gcc_unreachable ();
@@ -205,12 +194,6 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode)
       return TARGET_HTM;
     case ENB_MMA:
       return TARGET_MMA;
-    case ENB_FUTURE:
-      return TARGET_FUTURE;
-    case ENB_FUTURE_64:
-      return TARGET_FUTURE && TARGET_POWERPC64;
-    case ENB_DM:
-      return TARGET_DENSE_MATH;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 8b73e994558..e0d9f5adc97 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -139,8 +139,6 @@
 ;   endian   Needs special handling for endianness
 ;   ibmld    Restrict usage to the case when TFmode is IBM-128
 ;   ibm128   Restrict usage to the case where __ibm128 is supported or if ibmld
-;   future   Restrict usage to future instructions
-;   dm       Restrict usage to dense math
 ;
 ; Each attribute corresponds to extra processing required when
 ; the built-in is expanded.  All such special processing should
@@ -4110,12 +4108,3 @@
 
   void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
     STXVP nothing {mma,pair}
-
-[future]
-  const signed int __builtin_saturate_subtract32 (signed int, signed int);
-  SAT_SUBSI sat_subsi3 {}
-
-[future-64]
-  const signed long __builtin_saturate_subtract64 (signed long, signed long);
-  SAT_SUBDI sat_subdi3 {}
-
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc b/gcc/config/rs6000/rs6000-gen-builtins.cc
index daf7fff079e..a2f442ed90d 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.cc
+++ b/gcc/config/rs6000/rs6000-gen-builtins.cc
@@ -233,9 +233,6 @@ enum bif_stanza
  BSTZ_P10,
  BSTZ_P10_64,
  BSTZ_MMA,
- BSTZ_FUTURE,
- BSTZ_FUTURE_64,
- BSTZ_DM,
  NUMBIFSTANZAS
 };
 
@@ -269,10 +266,7 @@ static stanza_entry stanza_map[NUMBIFSTANZAS] =
     { "htm",		BSTZ_HTM	},
     { "power10",	BSTZ_P10	},
     { "power10-64",	BSTZ_P10_64	},
-    { "mma",		BSTZ_MMA	},
-    { "future",		BSTZ_FUTURE	},
-    { "future-64",	BSTZ_FUTURE_64	},
-    { "dm",		BSTZ_DM		},
+    { "mma",		BSTZ_MMA	}
   };
 
 static const char *enable_string[NUMBIFSTANZAS] =
@@ -297,10 +291,7 @@ static const char *enable_string[NUMBIFSTANZAS] =
     "ENB_HTM",
     "ENB_P10",
     "ENB_P10_64",
-    "ENB_MMA",
-    "ENB_FUTURE",
-    "ENB_FUTURE_64",
-    "ENB_DM",
+    "ENB_MMA"
   };
 
 /* Function modifiers provide special handling for const, pure, and fpmath
@@ -404,8 +395,6 @@ struct attrinfo
   bool isendian;
   bool isibmld;
   bool isibm128;
-  bool isfuture;
-  bool isdm;
 };
 
 /* Fields associated with a function prototype (bif or overload).  */
@@ -1488,8 +1477,7 @@ parse_bif_attrs (attrinfo *attrptr)
 	"ldvec = %d, stvec = %d, reve = %d, pred = %d, htm = %d, "
 	"htmspr = %d, htmcr = %d, mma = %d, quad = %d, pair = %d, "
 	"mmaint = %d, no32bit = %d, 32bit = %d, cpu = %d, ldstmask = %d, "
-	"lxvrse = %d, lxvrze = %d, endian = %d, ibmdld = %d, ibm128 = %d,",
-	"future = %d, dm = %d.\n",
+	"lxvrse = %d, lxvrze = %d, endian = %d, ibmdld = %d, ibm128 = %d.\n",
 	attrptr->isinit, attrptr->isset, attrptr->isextract,
 	attrptr->isnosoft, attrptr->isldvec, attrptr->isstvec,
 	attrptr->isreve, attrptr->ispred, attrptr->ishtm, attrptr->ishtmspr,
@@ -1497,7 +1485,7 @@ parse_bif_attrs (attrinfo *attrptr)
 	attrptr->ismmaint, attrptr->isno32bit, attrptr->is32bit,
 	attrptr->iscpu, attrptr->isldstmask, attrptr->islxvrse,
 	attrptr->islxvrze, attrptr->isendian, attrptr->isibmld,
-	attrptr->isibm128, attrptr->isfuture, attrptr->isdm);
+	attrptr->isibm128);
 #endif
 
   return PC_OK;
@@ -2269,10 +2257,7 @@ write_decls (void)
   fprintf (header_file, "  ENB_HTM,\n");
   fprintf (header_file, "  ENB_P10,\n");
   fprintf (header_file, "  ENB_P10_64,\n");
-  fprintf (header_file, "  ENB_MMA,\n");
-  fprintf (header_file, "  ENB_FUTURE,\n");
-  fprintf (header_file, "  ENB_FUTURE_64,\n");
-  fprintf (header_file, "  ENB_DM\n");
+  fprintf (header_file, "  ENB_MMA\n");
   fprintf (header_file, "};\n\n");
 
   fprintf (header_file, "#define PPC_MAXRESTROPNDS 3\n");
@@ -2316,8 +2301,6 @@ write_decls (void)
   fprintf (header_file, "#define bif_endian_bit\t\t(0x00200000)\n");
   fprintf (header_file, "#define bif_ibmld_bit\t\t(0x00400000)\n");
   fprintf (header_file, "#define bif_ibm128_bit\t\t(0x00800000)\n");
-  fprintf (header_file, "#define bif_future_bit\t\t(0x01000000)\n");
-  fprintf (header_file, "#define bif_dm_bit\t\t(0x02000000)\n");
   fprintf (header_file, "\n");
   fprintf (header_file,
 	   "#define bif_is_init(x)\t\t((x).bifattrs & bif_init_bit)\n");
@@ -2367,10 +2350,6 @@ write_decls (void)
 	   "#define bif_is_ibmld(x)\t((x).bifattrs & bif_ibmld_bit)\n");
   fprintf (header_file,
 	   "#define bif_is_ibm128(x)\t((x).bifattrs & bif_ibm128_bit)\n");
-  fprintf (header_file,
-	   "#define bif_is_future(x)\t((x).bifattrs & bif_future_bit)\n");
-  fprintf (header_file,
-	   "#define bif_is_dm(x)\t((x).bifattrs & bif_dm_bit)\n");
   fprintf (header_file, "\n");
 
   fprintf (header_file,
@@ -2569,10 +2548,6 @@ write_bif_static_init (void)
 	fprintf (init_file, " | bif_ibmld_bit");
       if (bifp->attrs.isibm128)
 	fprintf (init_file, " | bif_ibm128_bit");
-      if (bifp->attrs.isfuture)
-	fprintf (init_file, " | bif_future_bit");
-      if (bifp->attrs.isdm)
-	fprintf (init_file, " | bif_dm_bit");
       fprintf (init_file, ",\n");
       fprintf (init_file, "      /* restr_opnd */\t{%d, %d, %d},\n",
 	       bifp->proto.restr_opnd[0], bifp->proto.restr_opnd[1],
diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc
index 9b2f1b83b22..75e6f8803a5 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2811,7 +2811,6 @@ expand_block_move (rtx operands[], bool might_overlap)
 	  gen_func.mov = gen_vsx_movv2di_64bit;
 	}
       else if (TARGET_BLOCK_OPS_UNALIGNED_VSX
-	       && TARGET_POWERPC64
 	       && TARGET_POWER10 && bytes < 16
 	       && orig_bytes > 16
 	       && !(bytes == 1 || bytes == 2
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f9e231c16be..ee7651d9b43 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15654,66 +15654,6 @@
 }
   [(set_attr "type" "load")])
 \f
-;; Signed saturation.
-
-;; The subfus instruction is defined as: SUBFUS RT,L,RA,RB.  The extended
-;; mnemonic that we use (subdus and subwus) has the arguments RA and RB
-;; reversed (so it becomes a subtract instead of subtract from).
-
-(define_insn "sat_sub<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-	(ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-		      (match_operand:GPR 2 "gpc_reg_operand" "r")))]
-  "TARGET_FUTURE"
-  "sub<wd>us %0,%1,%2"
-  [(set_attr "type" "add")])
-
-(define_insn_and_split "*sat_sub<mode>3_dot"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
-				  (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:GPR 0 "=r,r"))]
-  "TARGET_FUTURE"
-  "@
-   sub<wd>us. %0,%1,%2
-   #"
-  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-	(ss_minus:GPR (match_dup 1)
-		      (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  ""
-  [(set_attr "type" "add")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-
-(define_insn_and_split "*sat_sub<mode>3_dot2"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
-				  (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
-	(ss_minus:GPR (match_dup 1)
-		      (match_dup 2)))]
-  "TARGET_FUTURE"
-  "@
-   sub<wd>us. %0,%1,%2
-   #"
-  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-	(ss_minus:GPR (match_dup 1)
-		      (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  ""
-  [(set_attr "type" "add")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-\f
 
 (include "sync.md")
 (include "vector.md")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 1ab8dc373c0..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5582,32 +5582,20 @@
   DONE;
 })
 
-;; Load VSX Vector with Length.  If we have lxvrl, we don't have to do an
-;; explicit shift left into a pseudo.
+;; Load VSX Vector with Length
 (define_expand "lxvl"
-  [(use (match_operand:V16QI 0 "vsx_register_operand"))
-   (use (match_operand:DI 1 "gpc_reg_operand"))
-   (use (match_operand:DI 2 "gpc_reg_operand"))]
+  [(set (match_dup 3)
+        (ashift:DI (match_operand:DI 2 "register_operand")
+                   (const_int 56)))
+   (set (match_operand:V16QI 0 "vsx_register_operand")
+	(unspec:V16QI
+	 [(match_operand:DI 1 "gpc_reg_operand")
+          (mem:V16QI (match_dup 1))
+	  (match_dup 3)]
+	 UNSPEC_LXVL))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
-  rtx len;
-
-  if (TARGET_FUTURE)
-    len = shift_len;
-  else
-    {
-      len = gen_reg_rtx (DImode);
-      emit_insn (gen_rtx_SET (len, shift_len));
-    }
-
-  rtx dest = operands[0];
-  rtx addr = operands[1];
-  rtx mem = gen_rtx_MEM (V16QImode, addr);
-  rtvec rv = gen_rtvec (3, addr, mem, len);
-  rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
-  emit_insn (gen_rtx_SET (dest, lxvl));
-  DONE;
+  operands[3] = gen_reg_rtx (DImode);
 })
 
 (define_insn "*lxvl"
@@ -5631,34 +5619,6 @@
   "lxvll %x0,%1,%2"
   [(set_attr "type" "vecload")])
 
-;; For lxvrl and lxvrll, use the combiner to eliminate the shift.  The
-;; define_expand for lxvl will already incorporate the shift in generating the
-;; insn.  The lxvll buitl-in function required the user to have already done
-;; the shift.  Defining lxvrll this way, will optimize cases where the user has
-;; done the shift immediately before the built-in.
-(define_insn "*lxvrl"
-  [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
-	(unspec:V16QI
-	 [(match_operand:DI 1 "gpc_reg_operand" "b")
-	  (mem:V16QI (match_dup 1))
-	  (ashift:DI (match_operand:DI 2 "register_operand" "r")
-		     (const_int 56))]
-	 UNSPEC_LXVL))]
-  "TARGET_FUTURE && TARGET_64BIT"
-  "lxvrl %x0,%1,%2"
-  [(set_attr "type" "vecload")])
-
-(define_insn "*lxvrll"
-  [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
-	(unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b")
-                       (mem:V16QI (match_dup 1))
-		       (ashift:DI (match_operand:DI 2 "register_operand" "r")
-				  (const_int 56))]
-		      UNSPEC_LXVLL))]
-  "TARGET_FUTURE"
-  "lxvrll %x0,%1,%2"
-  [(set_attr "type" "vecload")])
-
 ;; Expand for builtin xl_len_r
 (define_expand "xl_len_r"
   [(match_operand:V16QI 0 "vsx_register_operand")
@@ -5690,29 +5650,18 @@
 
 ;; Store VSX Vector with Length
 (define_expand "stxvl"
-  [(use (match_operand:V16QI 0 "vsx_register_operand"))
-   (use (match_operand:DI 1 "gpc_reg_operand"))
-   (use (match_operand:DI 2 "gpc_reg_operand"))]
+  [(set (match_dup 3)
+	(ashift:DI (match_operand:DI 2 "register_operand")
+		   (const_int 56)))
+   (set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand"))
+	(unspec:V16QI
+	 [(match_operand:V16QI 0 "vsx_register_operand")
+	  (mem:V16QI (match_dup 1))
+	  (match_dup 3)]
+	 UNSPEC_STXVL))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
-  rtx len;
-
-  if (TARGET_FUTURE)
-    len = shift_len;
-  else
-    {
-      len = gen_reg_rtx (DImode);
-      emit_insn (gen_rtx_SET (len, shift_len));
-    }
-
-  rtx src = operands[0];
-  rtx addr = operands[1];
-  rtx mem = gen_rtx_MEM (V16QImode, addr);
-  rtvec rv = gen_rtvec (3, src, mem, len);
-  rtx stxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_STXVL);
-  emit_insn (gen_rtx_SET (mem, stxvl));
-  DONE;
+  operands[3] = gen_reg_rtx (DImode);
 })
 
 ;; Define optab for vector access with length vectorization exploitation.
@@ -5756,35 +5705,6 @@
   "stxvl %x0,%1,%2"
   [(set_attr "type" "vecstore")])
 
-;; For stxvrl and stxvrll, use the combiner to eliminate the shift.  The
-;; define_expand for stxvl will already incorporate the shift in generating the
-;; insn.  The stxvll buitl-in function required the user to have already done
-;; the shift.  Defining stxvrll this way, will optimize cases where the user
-;; has done the shift immediately before the built-in.
-
-(define_insn "*stxvrl"
-  [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
-	(unspec:V16QI
-	 [(match_operand:V16QI 0 "vsx_register_operand" "wa")
-	  (mem:V16QI (match_dup 1))
-	  (ashift:DI (match_operand:DI 2 "register_operand" "r")
-		     (const_int 56))]
-	 UNSPEC_STXVL))]
-  "TARGET_FUTURE && TARGET_64BIT"
-  "stxvrl %x0,%1,%2"
-  [(set_attr "type" "vecstore")])
-
-(define_insn "*stxvrll"
-  [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
-	(unspec:V16QI [(match_operand:V16QI 0 "vsx_register_operand" "wa")
-		       (mem:V16QI (match_dup 1))
-		       (ashift:DI (match_operand:DI 2 "register_operand" "r")
-				  (const_int 56))]
-	              UNSPEC_STXVLL))]
-  "TARGET_FUTURE"
-  "stxvrll %x0,%1,%2"
-  [(set_attr "type" "vecstore")])
-
 ;; Expand for builtin xst_len_r
 (define_expand "xst_len_r"
   [(match_operand:V16QI 0 "vsx_register_operand" "=wa")
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index a6d25b5b618..5a026c4b48c 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -17839,7 +17839,6 @@ Disable global interrupt.
 * Basic PowerPC Built-in Functions Available on ISA 2.07::
 * Basic PowerPC Built-in Functions Available on ISA 3.0::
 * Basic PowerPC Built-in Functions Available on ISA 3.1::
-* Basic Built-in Functions that may be available on future PowerPCs::
 @end menu
 
 This section describes PowerPC built-in functions that do not require
@@ -18497,29 +18496,6 @@ ISA 3.1 @code{stxvrbx}, @code{stxvrhx}, @code{stxvrwx}, and @code{stxvrdx}
 instructions.
 @findex vec_xst_trunc
 
-@node Basic Built-in Functions that may be available on future PowerPCs
-@subsubsection Potential future PowerPC Built-in Functions
-
-The built-in functions described in this section may be available on
-future PowerPC processors.  At present, these built-ins exist to
-allowing testing of new instructions.  There is no guarantee that
-these instructions will actually be implemented.
-
-The following built-in functions are available on Linux 64-bit systems
-that use a potential future instruction set (@option{-mcpu=future}):
-
-@table @code
-@item int __builtin_saturate_subtract32 (int, int)
-Subtract the second operand from the first operand.  If the value
-would be less than 0, then the result is 0 instead of the negative
-value of the subtraction.
-
-@item long __builtin_saturate_subtract64 (long, long)
-Subtract the second operand from the first operand.  If the value
-would be less than 0, then the result is 0 instead of the negative
-value of the subtraction.
-@end table
-
 @node PowerPC AltiVec/VSX Built-in Functions
 @subsection PowerPC AltiVec/VSX Built-in Functions
 
diff --git a/gcc/testsuite/gcc.target/powerpc/lxvrl.c b/gcc/testsuite/gcc.target/powerpc/lxvrl.c
deleted file mode 100644
index 71854c50c91..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/lxvrl.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the lxvrl and stxvrl instructions are generated for
-   -mcpu=future on memory copy operations.  */
-
-#ifndef VSIZE
-#define VSIZE 2
-#endif
-
-#ifndef LSIZE
-#define LSIZE 5
-#endif
-
-struct foo {
-  vector unsigned char vc[VSIZE];
-  unsigned char leftover[LSIZE];
-};
-
-void memcpy_ptr (struct foo *p, struct foo *q)
-{
-  __builtin_memcpy ((void *) p,		/* lxvrl and stxvrl.  */
-		    (void *) q,
-		    (sizeof (vector unsigned char) * VSIZE) + LSIZE);
-}
-
-/* { dg-final { scan-assembler     {\mlxvrl\M}  } } */
-/* { dg-final { scan-assembler     {\mstxvrl\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvl\M}   } } */
-/* { dg-final { scan-assembler-not {\mstxvl\M}  } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/subfus-1.c b/gcc/testsuite/gcc.target/powerpc/subfus-1.c
deleted file mode 100644
index 535e7f8483d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/subfus-1.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the saturating subtract built-in generates subwus for 32-bit
-   subtracts.  */
-
-int do_sat_int  (int  a, int  b)
-{
-  return __builtin_saturate_subtract32 (a, b);		/* subwus  */
-}
-
-int do_sat_int_dot  (int  a, int  b, int  *p)
-{
-  int  r = __builtin_saturate_subtract32 (a, b);	/* subwus.  */
-  if (r == 0)
-    *p = 0;
-
-  return r;
-}
-
-void do_sat_int_dot2  (int  a, int  b, int  *p, int *q)
-{
-  if (__builtin_saturate_subtract32 (a, b))		/* subwus.  */
-    *p = 0;
-
-  *q = a + b;
-  return;
-}
-
-/* { dg-final { scan-assembler     {\msubwus\M} } } */
-/* { dg-final { scan-assembler-not {\msubf\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/subfus-2.c b/gcc/testsuite/gcc.target/powerpc/subfus-2.c
deleted file mode 100644
index b68e66dd2b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/subfus-2.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the saturating subtract built-in generates subwus for 64-bit
-   subtracts.  */
-
-long do_sat_long  (long  a, long  b)
-{
-  return __builtin_saturate_subtract64 (a, b);		/* subwus  */
-}
-
-long do_sat_long_dot  (long  a, long  b, long  *p)
-{
-  long  r = __builtin_saturate_subtract64 (a, b);	/* subwus.  */
-  if (r == 0)
-    *p = 0;
-
-  return r;
-}
-
-void do_sat_long_dot2  (long  a, long  b, long  *p, long *q)
-{
-  if (__builtin_saturate_subtract64 (a, b))		/* subwus.  */
-    *p = 0;
-
-  *q = a + b;
-  return;
-}
-
-/* { dg-final { scan-assembler     {\msubdus\M} } } */
-/* { dg-final { scan-assembler-not {\msubf\M}   } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 47adf407f83..9586ed3ae47 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6581,8 +6581,8 @@ proc check_effective_target_power10_ok { } {
     }
 }
 
-# Return 1 if this is a PowerPC target supporting -mcpu=future which enables
-# the dense math operations.
+# Return 1 if this is a PowerPC target supporting -mcpu=future or -mdense-math
+# which enables the dense math operations.
 proc check_effective_target_powerpc_dense_math_ok { } {
 	return [check_no_compiler_messages_nocache powerpc_dense_math_ok assembly {
 		__vector_quad vq;
@@ -6600,18 +6600,6 @@ proc check_effective_target_powerpc_dense_math_ok { } {
 	} "-mcpu=future"]
 }
 
-# Return 1 if this is a PowerPC target supporting -mcpu=future which enables
-# the saturating subtract instruction.
-proc check_effective_target_powerpc_future_ok { } {
-	return [check_no_compiler_messages powerpc_future_ok object {
-	    #ifndef _ARCH_PWR_FUTURE
-	    #error "not -mcpu=future"
-	    #else
-	    int dummy;
-	    #endif
-	} "-mcpu=future"]
-}
-
 # Return 1 if this is a PowerPC target supporting -mfloat128 via either
 # software emulation on power7/power8 systems or hardware support on power9.