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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/dmf008)] PowerPC: Add support for 1, 024 bit DMR registers.
Date: Sat, 4 Feb 2023 02:51:35 +0000 (GMT) [thread overview]
Message-ID: <20230204025135.698413858C5F@sourceware.org> (raw)
https://gcc.gnu.org/g:0c16dc66c66ed4232748ba5a14b04d8fce2b0e9f
commit 0c16dc66c66ed4232748ba5a14b04d8fce2b0e9f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Feb 3 21:51:13 2023 -0500
PowerPC: Add support for 1,024 bit DMR registers.
This patch changes TDO to V8TI in order to work around the restriction on GCC 13
that the precision size field is 10 bits.
2023-02-03 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/mma.md (movv8ti): Replace TDOmode with V8TImode.
Replace all tdo named functions with v8ti.
(movtdo): Likewise.
(movtv8ti_insert512_upper): Likewise.
(movtdo_insert512_upper): Likewise.
(movv8ti_insert512_lower): Likewise.
(movtdo_insert512_lower): Likewise.
(movv8ti_extract512): Likewise.
(movtdo_extract512): Likewise.
(reload_dmr_from_memory): Likewise.
(reload_dmr_to_memory): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Likewise.
* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Likewise.
(rs6000_function_arg): Likewise.
* config/rs6000/rs6000-modes.def (V8TImode): Likewise.
(TDOmode): Likewise.
* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_hard_regno_mode_ok): Likewise.
(rs6000_modes_tieable_p): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_secondary_reload_class): Likewise.
(rs6000_dmr_register_move_cost): Likewise.
(rs6000_split_multireg_move): Likewise.
(rs6000_invalid_conversion): Likewise.
* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Likewise.
Diff:
---
gcc/config/rs6000/mma.md | 72 ++++++++++++++++++-------------------
gcc/config/rs6000/rs6000-builtin.cc | 8 ++---
gcc/config/rs6000/rs6000-call.cc | 4 +--
gcc/config/rs6000/rs6000-modes.def | 5 ++-
gcc/config/rs6000/rs6000.cc | 58 +++++++++++++++---------------
gcc/config/rs6000/rs6000.h | 2 +-
6 files changed, 76 insertions(+), 73 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 0233c7b304a..dc42731e4cf 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -879,22 +879,22 @@
(set_attr "isa" "dm,not_dm,not_dm")])
\f
-;; TDOmode (i.e. __dmr).
-(define_expand "movtdo"
- [(set (match_operand:TDO 0 "nonimmediate_operand")
- (match_operand:TDO 1 "input_operand"))]
+;; V8TImode (i.e. __dmr).
+(define_expand "movv8ti"
+ [(set (match_operand:V8TI 0 "nonimmediate_operand")
+ (match_operand:V8TI 1 "input_operand"))]
"TARGET_DENSE_MATH"
{
- rs6000_emit_move (operands[0], operands[1], TDOmode);
+ rs6000_emit_move (operands[0], operands[1], V8TImode);
DONE;
})
-(define_insn_and_split "*movtdo"
- [(set (match_operand:TDO 0 "nonimmediate_operand" "=wa,m,wa,wD,wD,wa")
- (match_operand:TDO 1 "input_operand" "m,wa,wa,wa,wD,wD"))]
+(define_insn_and_split "*movv8ti"
+ [(set (match_operand:V8TI 0 "nonimmediate_operand" "=wa,m,wa,wD,wD,wa")
+ (match_operand:V8TI 1 "input_operand" "m,wa,wa,wa,wD,wD"))]
"TARGET_DENSE_MATH
- && (gpc_reg_operand (operands[0], TDOmode)
- || gpc_reg_operand (operands[1], TDOmode))"
+ && (gpc_reg_operand (operands[0], V8TImode)
+ || gpc_reg_operand (operands[1], V8TImode))"
"@
#
#
@@ -903,7 +903,7 @@
dmmr %0,%1
#"
"&& reload_completed
- && (!dmr_operand (operands[0], TDOmode) || !dmr_operand (operands[1], TDOmode))"
+ && (!dmr_operand (operands[0], V8TImode) || !dmr_operand (operands[1], V8TImode))"
[(const_int 0)]
{
rtx op0 = operands[0];
@@ -918,8 +918,8 @@
{
rtx op1_upper = gen_rtx_REG (XOmode, regno1);
rtx op1_lower = gen_rtx_REG (XOmode, regno1 + 4);
- emit_insn (gen_movtdo_insert512_upper (op0, op1_upper));
- emit_insn (gen_movtdo_insert512_lower (op0, op0, op1_lower));
+ emit_insn (gen_movv8ti_insert512_upper (op0, op1_upper));
+ emit_insn (gen_movv8ti_insert512_lower (op0, op0, op1_lower));
DONE;
}
@@ -927,8 +927,8 @@
{
rtx op0_upper = gen_rtx_REG (XOmode, regno0);
rtx op0_lower = gen_rtx_REG (XOmode, regno0 + 4);
- emit_insn (gen_movtdo_extract512 (op0_upper, op1, const0_rtx));
- emit_insn (gen_movtdo_extract512 (op0_lower, op1, const1_rtx));
+ emit_insn (gen_movv8ti_extract512 (op0_upper, op1, const0_rtx));
+ emit_insn (gen_movv8ti_extract512 (op0_lower, op1, const1_rtx));
DONE;
}
}
@@ -942,28 +942,28 @@
;; Move from VSX registers to DMR registers via two insert 512 bit
;; instructions.
-(define_insn "movtdo_insert512_upper"
- [(set (match_operand:TDO 0 "dmr_operand" "=wD")
- (unspec:TDO [(match_operand:XO 1 "vsx_register_operand" "wa")]
- UNSPEC_DM_INSERT512_UPPER))]
+(define_insn "movv8ti_insert512_upper"
+ [(set (match_operand:V8TI 0 "dmr_operand" "=wD")
+ (unspec:V8TI [(match_operand:XO 1 "vsx_register_operand" "wa")]
+ UNSPEC_DM_INSERT512_UPPER))]
"TARGET_DENSE_MATH"
"dmxxinstdmr512 %0,%1,%Y1,0"
[(set_attr "type" "mma")])
-(define_insn "movtdo_insert512_lower"
- [(set (match_operand:TDO 0 "dmr_operand" "=wD")
- (unspec:TDO [(match_operand:TDO 1 "dmr_operand" "0")
- (match_operand:XO 2 "vsx_register_operand" "wa")]
- UNSPEC_DM_INSERT512_LOWER))]
+(define_insn "movv8ti_insert512_lower"
+ [(set (match_operand:V8TI 0 "dmr_operand" "=wD")
+ (unspec:V8TI [(match_operand:V8TI 1 "dmr_operand" "0")
+ (match_operand:XO 2 "vsx_register_operand" "wa")]
+ UNSPEC_DM_INSERT512_LOWER))]
"TARGET_DENSE_MATH"
"dmxxinstdmr512 %0,%2,%Y2,1"
[(set_attr "type" "mma")])
;; Move from DMR registers to VSX registers via two extract 512 bit
;; instructions.
-(define_insn "movtdo_extract512"
+(define_insn "movv8ti_extract512"
[(set (match_operand:XO 0 "vsx_register_operand" "=wa")
- (unspec:XO [(match_operand:TDO 1 "dmr_operand" "wD")
+ (unspec:XO [(match_operand:V8TI 1 "dmr_operand" "wD")
(match_operand 2 "const_0_to_1_operand" "n")]
UNSPEC_DM_EXTRACT512))]
"TARGET_DENSE_MATH"
@@ -972,9 +972,9 @@
;; Reload DMR registers from memory
(define_insn_and_split "reload_dmr_from_memory"
- [(set (match_operand:TDO 0 "dmr_operand" "=wD")
- (unspec:TDO [(match_operand:TDO 1 "memory_operand" "m")]
- UNSPEC_DMR_RELOAD_FROM_MEMORY))
+ [(set (match_operand:V8TI 0 "dmr_operand" "=wD")
+ (unspec:V8TI [(match_operand:V8TI 1 "memory_operand" "m")]
+ UNSPEC_DMR_RELOAD_FROM_MEMORY))
(clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))]
"TARGET_DENSE_MATH"
"#"
@@ -988,10 +988,10 @@
rtx mem_lower = adjust_address (src, XOmode, BYTES_BIG_ENDIAN ? 32 : 0);
emit_move_insn (tmp, mem_upper);
- emit_insn (gen_movtdo_insert512_upper (dest, tmp));
+ emit_insn (gen_movv8ti_insert512_upper (dest, tmp));
emit_move_insn (tmp, mem_lower);
- emit_insn (gen_movtdo_insert512_lower (dest, dest, tmp));
+ emit_insn (gen_movv8ti_insert512_lower (dest, dest, tmp));
DONE;
}
[(set_attr "length" "16")
@@ -1000,9 +1000,9 @@
;; Reload dense math registers to memory
(define_insn_and_split "reload_dmr_to_memory"
- [(set (match_operand:TDO 0 "memory_operand" "=m")
- (unspec:TDO [(match_operand:TDO 1 "dmr_operand" "wD")]
- UNSPEC_DMR_RELOAD_TO_MEMORY))
+ [(set (match_operand:V8TI 0 "memory_operand" "=m")
+ (unspec:V8TI [(match_operand:V8TI 1 "dmr_operand" "wD")]
+ UNSPEC_DMR_RELOAD_TO_MEMORY))
(clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))]
"TARGET_DENSE_MATH"
"#"
@@ -1015,10 +1015,10 @@
rtx mem_upper = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 0 : 32);
rtx mem_lower = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 32 : 0);
- emit_insn (gen_movtdo_extract512 (tmp, src, const0_rtx));
+ emit_insn (gen_movv8ti_extract512 (tmp, src, const0_rtx));
emit_move_insn (mem_upper, tmp);
- emit_insn (gen_movtdo_extract512 (tmp, src, const1_rtx));
+ emit_insn (gen_movv8ti_extract512 (tmp, src, const1_rtx));
emit_move_insn (mem_lower, tmp);
DONE;
}
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index b9b0b2d52d0..79f0312b625 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -801,10 +801,10 @@ rs6000_init_builtins (void)
ptr_vector_quad_type_node = build_pointer_type (t);
dmr_type_node = make_node (OPAQUE_TYPE);
- SET_TYPE_MODE (dmr_type_node, TDOmode);
- TYPE_SIZE (dmr_type_node) = bitsize_int (GET_MODE_BITSIZE (TDOmode));
- TYPE_PRECISION (dmr_type_node) = GET_MODE_BITSIZE (TDOmode);
- TYPE_SIZE_UNIT (dmr_type_node) = size_int (GET_MODE_SIZE (TDOmode));
+ SET_TYPE_MODE (dmr_type_node, V8TImode);
+ TYPE_SIZE (dmr_type_node) = bitsize_int (GET_MODE_BITSIZE (V8TImode));
+ TYPE_PRECISION (dmr_type_node) = GET_MODE_BITSIZE (V8TImode);
+ TYPE_SIZE_UNIT (dmr_type_node) = size_int (GET_MODE_SIZE (V8TImode));
SET_TYPE_ALIGN (dmr_type_node, 512);
TYPE_USER_ALIGN (dmr_type_node) = 0;
lang_hooks.types.register_builtin_type (dmr_type_node, "__dmr");
diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc
index dcf5b470766..f109c16bbe0 100644
--- a/gcc/config/rs6000/rs6000-call.cc
+++ b/gcc/config/rs6000/rs6000-call.cc
@@ -438,7 +438,7 @@ rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
&& !cfun->machine->mma_return_type_error
&& TREE_TYPE (cfun->decl) == fntype
&& (TYPE_MODE (type) == OOmode || TYPE_MODE (type) == XOmode
- || TYPE_MODE (type) == TDOmode))
+ || TYPE_MODE (type) == V8TImode))
{
/* Record we have now handled function CFUN, so the next time we
are called, we do not re-report the same error. */
@@ -1642,7 +1642,7 @@ rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
return NULL_RTX;
}
- if (mode == TDOmode)
+ if (mode == V8TImode)
{
if (TYPE_CANONICAL (type) != NULL_TREE)
type = TYPE_CANONICAL (type);
diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index d36bde9d2a0..a0ae087f4f7 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -88,5 +88,8 @@ OPAQUE_MODE (OO, 32);
OPAQUE_MODE (XO, 64);
/* Modes used by __dmr. */
-OPAQUE_MODE (TDO, 128);
+/* OPAQUE_MODE (TDO, 128); */
+VECTOR_MODE (INT, TI, 8); /* V8TI */
+
+
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 58ee643260f..2e0dfea5c16 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1843,7 +1843,7 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
if (FP_REGNO_P (regno))
reg_size = (VECTOR_MEM_VSX_P (mode)
|| VECTOR_ALIGNMENT_P (mode)
- || mode == TDOmode
+ || mode == V8TImode
? UNITS_PER_VSX_WORD
: UNITS_PER_FP_WORD);
@@ -1904,7 +1904,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
/* Dense math register modes need DMR registers or VSX registers divisible by
2. We need to make sure we don't cross between the boundary of FPRs and
traditional Altiviec registers. */
- if (mode == TDOmode)
+ if (mode == V8TImode)
{
if (!TARGET_DENSE_MATH)
return 0;
@@ -1921,7 +1921,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
return 0;
}
- /* No other types other than XOmode or TDOmode can go in DMRs. */
+ /* No other types other than XOmode or V8TImode can go in DMRs. */
if (DMR_REGNO_P (regno))
return 0;
@@ -2030,7 +2030,7 @@ rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
57744).
Similarly, don't allow OOmode (vector pair), XOmode (vector quad), or
- TDOmode (dmr register) to pair with anything else. Vector pairs are
+ V8TImode (dmr register) to pair with anything else. Vector pairs are
restricted to even/odd VSX registers. Without dense math, vector quads are
limited to FPR registers divisible by 4. With dense math, vector quads are
limited to even VSX registers or DMR registers.
@@ -2042,8 +2042,8 @@ static bool
rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode
- || mode1 == TDOmode || mode2 == PTImode || mode2 == OOmode
- || mode2 == XOmode || mode2 == TDOmode)
+ || mode1 == V8TImode || mode2 == PTImode || mode2 == OOmode
+ || mode2 == XOmode || mode2 == V8TImode)
return mode1 == mode2;
if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
@@ -2334,7 +2334,7 @@ rs6000_debug_reg_global (void)
V4DFmode,
OOmode,
XOmode,
- TDOmode,
+ V8TImode,
CCmode,
CCUNSmode,
CCEQmode,
@@ -2700,7 +2700,7 @@ rs6000_setup_reg_addr_masks (void)
/* Special case DMR registers. */
if (rc == RELOAD_REG_DMR)
{
- if (TARGET_DENSE_MATH && (m2 == XOmode || m2 == TDOmode))
+ if (TARGET_DENSE_MATH && (m2 == XOmode || m2 == V8TImode))
{
addr_mask = RELOAD_REG_VALID;
reg_addr[m].addr_mask[rc] = addr_mask;
@@ -2810,7 +2810,7 @@ rs6000_setup_reg_addr_masks (void)
since it will be broken into two vector moves. Vector quads and
1,024 bit DMR values can only do offset loads. */
else if ((addr_mask != 0) && TARGET_MMA
- && (m2 == OOmode || m2 == XOmode || m2 == TDOmode))
+ && (m2 == OOmode || m2 == XOmode || m2 == V8TImode))
{
addr_mask |= RELOAD_REG_OFFSET;
if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
@@ -3041,9 +3041,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
/* Add support for 1,024 bit DMR registers. */
if (TARGET_DENSE_MATH)
{
- rs6000_vector_unit[TDOmode] = VECTOR_NONE;
- rs6000_vector_mem[TDOmode] = VECTOR_VSX;
- rs6000_vector_align[TDOmode] = 512;
+ rs6000_vector_unit[V8TImode] = VECTOR_NONE;
+ rs6000_vector_mem[V8TImode] = VECTOR_VSX;
+ rs6000_vector_align[V8TImode] = 512;
}
/* Register class constraints for the constraints that depend on compile
@@ -3261,8 +3261,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DENSE_MATH)
{
- reg_addr[TDOmode].reload_load = CODE_FOR_reload_dmr_from_memory;
- reg_addr[TDOmode].reload_store = CODE_FOR_reload_dmr_to_memory;
+ reg_addr[V8TImode].reload_load = CODE_FOR_reload_dmr_from_memory;
+ reg_addr[V8TImode].reload_store = CODE_FOR_reload_dmr_to_memory;
}
/* Precalculate HARD_REGNO_NREGS. */
@@ -8768,7 +8768,7 @@ reg_offset_addressing_ok_p (machine_mode mode)
case E_XOmode:
return TARGET_MMA;
- case E_TDOmode:
+ case E_V8TImode:
return TARGET_DENSE_MATH;
case E_SDmode:
@@ -11052,7 +11052,7 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
(mode == OOmode) ? "__vector_pair" : "__vector_quad");
break;
- case E_TDOmode:
+ case E_V8TImode:
if (CONST_INT_P (operands[1]))
error ("%qs is an opaque type, and you cannot set it to constants",
"__dmr");
@@ -12512,7 +12512,7 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
/* We can transfer between VSX registers and DMR registers without needing
extra registers. */
- if (TARGET_DENSE_MATH && (mode == XOmode || mode == TDOmode)
+ if (TARGET_DENSE_MATH && (mode == XOmode || mode == V8TImode)
&& ((to_type == DMR_REG_TYPE && from_type == VSX_REG_TYPE)
|| (to_type == VSX_REG_TYPE && from_type == DMR_REG_TYPE)))
return true;
@@ -13313,7 +13313,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
if (mode == XOmode)
return TARGET_DENSE_MATH ? VSX_REGS : FLOAT_REGS;
- if (mode == TDOmode)
+ if (mode == V8TImode)
return VSX_REGS;
if (GET_MODE_CLASS (mode) == MODE_INT)
@@ -13440,7 +13440,7 @@ rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
regno = -1;
/* Dense math registers don't have loads or stores. We have to go through
- the VSX registers to load XOmode (vector quad) and TDOmode (dmr 1024
+ the VSX registers to load XOmode (vector quad) and V8TImode (dmr 1024
bit). */
if (TARGET_DENSE_MATH && rclass == DM_REGS)
return VSX_REGS;
@@ -22649,8 +22649,8 @@ rs6000_dmr_register_move_cost (machine_mode mode, reg_class_t rclass)
if (mode == XOmode)
return reg_move_base;
- /* __dmr (i.e. TDOmode) is transferred in 2 instructions. */
- else if (mode == TDOmode)
+ /* __dmr (i.e. V8TImode) is transferred in 2 instructions. */
+ else if (mode == V8TImode)
return reg_move_base * 2;
else
@@ -27350,7 +27350,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we have a vector quad register for MMA or DMR register for dense math,
and this is a load or store, see if we can use vector paired
load/stores. */
- if ((mode == XOmode || mode == TDOmode) && TARGET_MMA
+ if ((mode == XOmode || mode == V8TImode) && TARGET_MMA
&& (MEM_P (dst) || MEM_P (src)))
{
reg_mode = OOmode;
@@ -27358,7 +27358,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
}
/* If we have a vector pair/quad mode, split it into two/four separate
vectors. */
- else if (mode == OOmode || mode == XOmode || mode == TDOmode)
+ else if (mode == OOmode || mode == XOmode || mode == V8TImode)
reg_mode = V1TImode;
else if (FP_REGNO_P (reg))
reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
@@ -27410,7 +27410,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
the last register gets the first memory location. We also need to be
careful of using the right register numbers if we are splitting XO to
OO. */
- if (mode == OOmode || mode == XOmode || mode == TDOmode)
+ if (mode == OOmode || mode == XOmode || mode == V8TImode)
{
nregs = hard_regno_nregs (reg, mode);
int reg_mode_nregs = hard_regno_nregs (reg, reg_mode);
@@ -27547,7 +27547,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
overlap. */
int i;
/* XO/OO are opaque so cannot use subregs. */
- if (mode == OOmode || mode == XOmode || mode == TDOmode)
+ if (mode == OOmode || mode == XOmode || mode == V8TImode)
{
for (i = nregs - 1; i >= 0; i--)
{
@@ -27721,7 +27721,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
continue;
/* XO/OO are opaque so cannot use subregs. */
- if (mode == OOmode || mode == XOmode || mode == TDOmode)
+ if (mode == OOmode || mode == XOmode || mode == V8TImode)
{
rtx dst_i = gen_rtx_REG (reg_mode, REGNO (dst) + j);
rtx src_i = gen_rtx_REG (reg_mode, REGNO (src) + j);
@@ -28701,7 +28701,7 @@ rs6000_invalid_conversion (const_tree fromtype, const_tree totype)
if (frommode != tomode)
{
- /* Do not allow conversions to/from XOmode, OOmode, and TDOmode
+ /* Do not allow conversions to/from XOmode, OOmode, and V8TImode
types. */
if (frommode == XOmode)
return N_("invalid conversion from type %<__vector_quad%>");
@@ -28711,9 +28711,9 @@ rs6000_invalid_conversion (const_tree fromtype, const_tree totype)
return N_("invalid conversion from type %<__vector_pair%>");
if (tomode == OOmode)
return N_("invalid conversion to type %<__vector_pair%>");
- if (frommode == TDOmode)
+ if (frommode == V8TImode)
return N_("invalid conversion from type %<__dmr%>");
- if (tomode == TDOmode)
+ if (tomode == V8TImode)
return N_("invalid conversion to type %<__dmr%>");
}
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 823de897603..a8916a979f8 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1007,7 +1007,7 @@ enum data_align { align_abi, align_opt, align_both };
vectors in terms of loads and stores. */
#define VECTOR_ALIGNMENT_P(MODE) \
(FLOAT128_VECTOR_P (MODE) || (MODE) == OOmode || (MODE) == XOmode \
- || (MODE) == TDOmode)
+ || (MODE) == V8TImode)
#define ALTIVEC_VECTOR_MODE(MODE) \
((MODE) == V16QImode \
next reply other threads:[~2023-02-04 2:51 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-04 2:51 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-02-02 20:26 Michael Meissner
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