From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id BC22938582B0; Sun, 12 Feb 2023 03:00:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BC22938582B0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676170831; bh=lPE4nJCXaAlXeEz4CMOuSJq4antlVUyhmMakLsk/o+8=; h=From:To:Subject:Date:From; b=GkKHhrAlK9BrTmTOeIYj2cqKDU4TDQOUwQRtybl8XcAd/DLjfLeodZxtk/nfDqDpv QBhBzF9kxtN/mhtOQG3iLdwbtzItNpbOzpW5dkh+eU2pWlQ1ANgJv8SPT8VbmUrgP4 dnM7bqxgQRAuonSvZilRTh3JkflHNOgS6ElXEpHM= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5825] RISC-V: Add vnot.v C++ API tests X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 779e441103e834c9b973ae25956e4546543aec0a X-Git-Newrev: 4170a0f021faa12541dc02838d928844ce8351f8 Message-Id: <20230212030031.BC22938582B0@sourceware.org> Date: Sun, 12 Feb 2023 03:00:31 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4170a0f021faa12541dc02838d928844ce8351f8 commit r13-5825-g4170a0f021faa12541dc02838d928844ce8351f8 Author: Ju-Zhe Zhong Date: Sat Feb 4 07:26:41 2023 +0800 RISC-V: Add vnot.v C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vnot_v-1.C: New test. * g++.target/riscv/rvv/base/vnot_v-2.C: New test. * g++.target/riscv/rvv/base/vnot_v-3.C: New test. * g++.target/riscv/rvv/base/vnot_v_mu-1.C: New test. * g++.target/riscv/rvv/base/vnot_v_mu-2.C: New test. * g++.target/riscv/rvv/base/vnot_v_mu-3.C: New test. * g++.target/riscv/rvv/base/vnot_v_tu-1.C: New test. * g++.target/riscv/rvv/base/vnot_v_tu-2.C: New test. * g++.target/riscv/rvv/base/vnot_v_tu-3.C: New test. * g++.target/riscv/rvv/base/vnot_v_tum-1.C: New test. * g++.target/riscv/rvv/base/vnot_v_tum-2.C: New test. * g++.target/riscv/rvv/base/vnot_v_tum-3.C: New test. * g++.target/riscv/rvv/base/vnot_v_tumu-1.C: New test. * g++.target/riscv/rvv/base/vnot_v_tumu-2.C: New test. * g++.target/riscv/rvv/base/vnot_v_tumu-3.C: New test. Diff: --- gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tumu-3.C | 160 +++++++++++ 15 files changed, 2862 insertions(+) diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C new file mode 100644 index 00000000000..23e6f92c8c9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot(vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8mf4_t test___riscv_vnot(vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8mf2_t test___riscv_vnot(vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8m1_t test___riscv_vnot(vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8m2_t test___riscv_vnot(vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8m4_t test___riscv_vnot(vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8m8_t test___riscv_vnot(vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16mf4_t test___riscv_vnot(vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16mf2_t test___riscv_vnot(vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16m1_t test___riscv_vnot(vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16m2_t test___riscv_vnot(vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16m4_t test___riscv_vnot(vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16m8_t test___riscv_vnot(vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32mf2_t test___riscv_vnot(vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32m1_t test___riscv_vnot(vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32m2_t test___riscv_vnot(vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32m4_t test___riscv_vnot(vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32m8_t test___riscv_vnot(vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint64m1_t test___riscv_vnot(vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint64m2_t test___riscv_vnot(vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint64m4_t test___riscv_vnot(vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint64m8_t test___riscv_vnot(vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8mf8_t test___riscv_vnot(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8mf4_t test___riscv_vnot(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8mf2_t test___riscv_vnot(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8m1_t test___riscv_vnot(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8m2_t test___riscv_vnot(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8m4_t test___riscv_vnot(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8m8_t test___riscv_vnot(vbool1_t mask,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16mf4_t test___riscv_vnot(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16mf2_t test___riscv_vnot(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16m1_t test___riscv_vnot(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16m2_t test___riscv_vnot(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16m4_t test___riscv_vnot(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16m8_t test___riscv_vnot(vbool2_t mask,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32mf2_t test___riscv_vnot(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32m1_t test___riscv_vnot(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32m2_t test___riscv_vnot(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32m4_t test___riscv_vnot(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32m8_t test___riscv_vnot(vbool4_t mask,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint64m1_t test___riscv_vnot(vbool64_t mask,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint64m2_t test___riscv_vnot(vbool32_t mask,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint64m4_t test___riscv_vnot(vbool16_t mask,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint64m8_t test___riscv_vnot(vbool8_t mask,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C new file mode 100644 index 00000000000..35426a06531 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot(vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8mf4_t test___riscv_vnot(vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8mf2_t test___riscv_vnot(vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8m1_t test___riscv_vnot(vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8m2_t test___riscv_vnot(vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8m4_t test___riscv_vnot(vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8m8_t test___riscv_vnot(vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16mf4_t test___riscv_vnot(vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16mf2_t test___riscv_vnot(vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16m1_t test___riscv_vnot(vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16m2_t test___riscv_vnot(vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16m4_t test___riscv_vnot(vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16m8_t test___riscv_vnot(vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32mf2_t test___riscv_vnot(vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32m1_t test___riscv_vnot(vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32m2_t test___riscv_vnot(vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32m4_t test___riscv_vnot(vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32m8_t test___riscv_vnot(vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint64m1_t test___riscv_vnot(vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint64m2_t test___riscv_vnot(vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint64m4_t test___riscv_vnot(vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint64m8_t test___riscv_vnot(vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8mf8_t test___riscv_vnot(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8mf4_t test___riscv_vnot(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8mf2_t test___riscv_vnot(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8m1_t test___riscv_vnot(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8m2_t test___riscv_vnot(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8m4_t test___riscv_vnot(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8m8_t test___riscv_vnot(vbool1_t mask,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16mf4_t test___riscv_vnot(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16mf2_t test___riscv_vnot(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16m1_t test___riscv_vnot(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16m2_t test___riscv_vnot(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16m4_t test___riscv_vnot(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16m8_t test___riscv_vnot(vbool2_t mask,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32mf2_t test___riscv_vnot(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32m1_t test___riscv_vnot(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32m2_t test___riscv_vnot(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32m4_t test___riscv_vnot(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32m8_t test___riscv_vnot(vbool4_t mask,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint64m1_t test___riscv_vnot(vbool64_t mask,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint64m2_t test___riscv_vnot(vbool32_t mask,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint64m4_t test___riscv_vnot(vbool16_t mask,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint64m8_t test___riscv_vnot(vbool8_t mask,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C new file mode 100644 index 00000000000..42fd5054ea0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot(vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8mf4_t test___riscv_vnot(vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8mf2_t test___riscv_vnot(vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8m1_t test___riscv_vnot(vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8m2_t test___riscv_vnot(vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8m4_t test___riscv_vnot(vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8m8_t test___riscv_vnot(vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16mf4_t test___riscv_vnot(vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16mf2_t test___riscv_vnot(vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16m1_t test___riscv_vnot(vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16m2_t test___riscv_vnot(vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16m4_t test___riscv_vnot(vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16m8_t test___riscv_vnot(vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32mf2_t test___riscv_vnot(vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32m1_t test___riscv_vnot(vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32m2_t test___riscv_vnot(vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32m4_t test___riscv_vnot(vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32m8_t test___riscv_vnot(vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint64m1_t test___riscv_vnot(vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint64m2_t test___riscv_vnot(vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint64m4_t test___riscv_vnot(vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint64m8_t test___riscv_vnot(vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8mf8_t test___riscv_vnot(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8mf4_t test___riscv_vnot(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8mf2_t test___riscv_vnot(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8m1_t test___riscv_vnot(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8m2_t test___riscv_vnot(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8m4_t test___riscv_vnot(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8m8_t test___riscv_vnot(vbool1_t mask,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16mf4_t test___riscv_vnot(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16mf2_t test___riscv_vnot(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16m1_t test___riscv_vnot(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16m2_t test___riscv_vnot(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16m4_t test___riscv_vnot(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16m8_t test___riscv_vnot(vbool2_t mask,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32mf2_t test___riscv_vnot(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32m1_t test___riscv_vnot(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32m2_t test___riscv_vnot(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32m4_t test___riscv_vnot(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32m8_t test___riscv_vnot(vbool4_t mask,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint64m1_t test___riscv_vnot(vbool64_t mask,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint64m2_t test___riscv_vnot(vbool32_t mask,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint64m4_t test___riscv_vnot(vbool16_t mask,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint64m8_t test___riscv_vnot(vbool8_t mask,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C new file mode 100644 index 00000000000..3fcbf02aed5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8mf4_t test___riscv_vnot_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8mf2_t test___riscv_vnot_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8m1_t test___riscv_vnot_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8m2_t test___riscv_vnot_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8m4_t test___riscv_vnot_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8m8_t test___riscv_vnot_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16mf4_t test___riscv_vnot_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vnot_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vnot_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vnot_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vnot_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vnot_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vnot_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vnot_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vnot_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vnot_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vnot_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vnot_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vnot_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vnot_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vnot_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C new file mode 100644 index 00000000000..5dde6117a43 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8mf4_t test___riscv_vnot_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8mf2_t test___riscv_vnot_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8m1_t test___riscv_vnot_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8m2_t test___riscv_vnot_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8m4_t test___riscv_vnot_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8m8_t test___riscv_vnot_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16mf4_t test___riscv_vnot_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vnot_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vnot_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vnot_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vnot_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vnot_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vnot_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vnot_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vnot_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vnot_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vnot_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vnot_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vnot_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vnot_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vnot_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C new file mode 100644 index 00000000000..c3637b98b66 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8mf4_t test___riscv_vnot_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8mf2_t test___riscv_vnot_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8m1_t test___riscv_vnot_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8m2_t test___riscv_vnot_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8m4_t test___riscv_vnot_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8m8_t test___riscv_vnot_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16mf4_t test___riscv_vnot_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vnot_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vnot_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vnot_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vnot_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vnot_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vnot_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vnot_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vnot_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vnot_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vnot_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vnot_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vnot_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vnot_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vnot_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C new file mode 100644 index 00000000000..25fb8e93c91 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8mf4_t test___riscv_vnot_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8mf2_t test___riscv_vnot_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8m1_t test___riscv_vnot_tu(vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8m2_t test___riscv_vnot_tu(vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8m4_t test___riscv_vnot_tu(vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8m8_t test___riscv_vnot_tu(vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16mf4_t test___riscv_vnot_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16mf2_t test___riscv_vnot_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16m1_t test___riscv_vnot_tu(vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16m2_t test___riscv_vnot_tu(vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16m4_t test___riscv_vnot_tu(vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16m8_t test___riscv_vnot_tu(vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32mf2_t test___riscv_vnot_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32m1_t test___riscv_vnot_tu(vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32m2_t test___riscv_vnot_tu(vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32m4_t test___riscv_vnot_tu(vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32m8_t test___riscv_vnot_tu(vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint64m1_t test___riscv_vnot_tu(vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint64m2_t test___riscv_vnot_tu(vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint64m4_t test___riscv_vnot_tu(vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint64m8_t test___riscv_vnot_tu(vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C new file mode 100644 index 00000000000..b05b86fce83 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8mf4_t test___riscv_vnot_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8mf2_t test___riscv_vnot_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8m1_t test___riscv_vnot_tu(vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8m2_t test___riscv_vnot_tu(vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8m4_t test___riscv_vnot_tu(vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8m8_t test___riscv_vnot_tu(vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16mf4_t test___riscv_vnot_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16mf2_t test___riscv_vnot_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16m1_t test___riscv_vnot_tu(vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16m2_t test___riscv_vnot_tu(vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16m4_t test___riscv_vnot_tu(vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16m8_t test___riscv_vnot_tu(vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32mf2_t test___riscv_vnot_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32m1_t test___riscv_vnot_tu(vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32m2_t test___riscv_vnot_tu(vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32m4_t test___riscv_vnot_tu(vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32m8_t test___riscv_vnot_tu(vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint64m1_t test___riscv_vnot_tu(vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint64m2_t test___riscv_vnot_tu(vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint64m4_t test___riscv_vnot_tu(vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint64m8_t test___riscv_vnot_tu(vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C new file mode 100644 index 00000000000..7048f9ecc99 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8mf4_t test___riscv_vnot_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8mf2_t test___riscv_vnot_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8m1_t test___riscv_vnot_tu(vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8m2_t test___riscv_vnot_tu(vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8m4_t test___riscv_vnot_tu(vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8m8_t test___riscv_vnot_tu(vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16mf4_t test___riscv_vnot_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16mf2_t test___riscv_vnot_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16m1_t test___riscv_vnot_tu(vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16m2_t test___riscv_vnot_tu(vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16m4_t test___riscv_vnot_tu(vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16m8_t test___riscv_vnot_tu(vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32mf2_t test___riscv_vnot_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32m1_t test___riscv_vnot_tu(vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32m2_t test___riscv_vnot_tu(vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32m4_t test___riscv_vnot_tu(vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32m8_t test___riscv_vnot_tu(vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint64m1_t test___riscv_vnot_tu(vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint64m2_t test___riscv_vnot_tu(vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint64m4_t test___riscv_vnot_tu(vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint64m8_t test___riscv_vnot_tu(vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C new file mode 100644 index 00000000000..151f6559f9f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8mf4_t test___riscv_vnot_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8mf2_t test___riscv_vnot_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8m1_t test___riscv_vnot_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8m2_t test___riscv_vnot_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8m4_t test___riscv_vnot_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8m8_t test___riscv_vnot_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16mf4_t test___riscv_vnot_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vnot_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vnot_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vnot_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vnot_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vnot_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vnot_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vnot_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vnot_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vnot_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vnot_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vnot_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vnot_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vnot_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vnot_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C new file mode 100644 index 00000000000..a9d767d88f4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8mf4_t test___riscv_vnot_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8mf2_t test___riscv_vnot_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8m1_t test___riscv_vnot_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8m2_t test___riscv_vnot_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8m4_t test___riscv_vnot_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8m8_t test___riscv_vnot_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16mf4_t test___riscv_vnot_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vnot_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vnot_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vnot_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vnot_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vnot_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vnot_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vnot_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vnot_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vnot_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vnot_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vnot_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vnot_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vnot_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vnot_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C new file mode 100644 index 00000000000..1d39bcc7349 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8mf4_t test___riscv_vnot_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8mf2_t test___riscv_vnot_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8m1_t test___riscv_vnot_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8m2_t test___riscv_vnot_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8m4_t test___riscv_vnot_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8m8_t test___riscv_vnot_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16mf4_t test___riscv_vnot_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vnot_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vnot_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vnot_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vnot_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vnot_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vnot_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vnot_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vnot_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vnot_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vnot_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vnot_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vnot_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vnot_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vnot_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C new file mode 100644 index 00000000000..9dfe96a8474 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8mf4_t test___riscv_vnot_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8mf2_t test___riscv_vnot_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8m1_t test___riscv_vnot_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8m2_t test___riscv_vnot_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8m4_t test___riscv_vnot_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8m8_t test___riscv_vnot_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16mf4_t test___riscv_vnot_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vnot_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vnot_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vnot_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vnot_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vnot_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vnot_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vnot_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vnot_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vnot_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vnot_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vnot_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vnot_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vnot_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vnot_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C new file mode 100644 index 00000000000..223b7ce3865 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8mf4_t test___riscv_vnot_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8mf2_t test___riscv_vnot_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8m1_t test___riscv_vnot_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8m2_t test___riscv_vnot_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8m4_t test___riscv_vnot_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8m8_t test___riscv_vnot_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16mf4_t test___riscv_vnot_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vnot_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vnot_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vnot_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vnot_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vnot_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vnot_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vnot_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vnot_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vnot_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vnot_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vnot_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vnot_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vnot_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vnot_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C new file mode 100644 index 00000000000..492595d74b1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8mf4_t test___riscv_vnot_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8mf2_t test___riscv_vnot_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8m1_t test___riscv_vnot_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8m2_t test___riscv_vnot_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8m4_t test___riscv_vnot_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8m8_t test___riscv_vnot_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16mf4_t test___riscv_vnot_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vnot_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vnot_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vnot_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vnot_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vnot_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vnot_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vnot_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vnot_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vnot_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vnot_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vnot_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vnot_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vnot_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vnot_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */