From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 2E55A385842E; Sun, 12 Feb 2023 03:33:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2E55A385842E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676172833; bh=kAxlvybz0etjIFq7BYGn7q0gORypUT9tgU7zVlpYRkA=; h=From:To:Subject:Date:From; b=R/tcX0DCZsSthbl3t6Hn7wl+t4GhLnlbLc18gf4i+SCE7LmJ4JU9cK+ORpzVnT1c/ ISaS807WFJJxqBd4CmwXsvcXvX7TPTqgEH9EhhBesmiwhAQXNi9eXFV9y1BVT9T5EY ia/F43JoMWg6NHnsS65kdGpO97Ar6lhbbrCJnAJI= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5854] RISC-V: Add vzext.vf4 C++ API tests X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 221f26c9624586b5cec6c5bb8c0a63e21359d1f6 X-Git-Newrev: 522d385831bf6ccdc34a82c3701ebaa2e3bc6b6a Message-Id: <20230212033353.2E55A385842E@sourceware.org> Date: Sun, 12 Feb 2023 03:33:53 +0000 (GMT) List-Id: https://gcc.gnu.org/g:522d385831bf6ccdc34a82c3701ebaa2e3bc6b6a commit r13-5854-g522d385831bf6ccdc34a82c3701ebaa2e3bc6b6a Author: Ju-Zhe Zhong Date: Mon Feb 6 13:23:27 2023 +0800 RISC-V: Add vzext.vf4 C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vzext_vf4-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_mu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_mu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_mu-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tu-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tum-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tum-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tum-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C: New test. Diff: --- .../g++.target/riscv/rvv/base/vzext_vf4-1.C | 132 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4-2.C | 132 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4-3.C | 132 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_mu-1.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_mu-2.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_mu-3.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tu-1.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tu-2.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tu-3.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tum-1.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tum-2.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tum-3.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C | 69 +++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C | 69 +++++++++++ 15 files changed, 1224 insertions(+) diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C new file mode 100644 index 00000000000..5875271fa88 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32mf2_t test___riscv_vzext_vf4(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-2.C new file mode 100644 index 00000000000..27022784040 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-2.C @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32mf2_t test___riscv_vzext_vf4(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-3.C new file mode 100644 index 00000000000..a7f36a35cfb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-3.C @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32mf2_t test___riscv_vzext_vf4(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-1.C new file mode 100644 index 00000000000..1692dfbdbee --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_mu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-2.C new file mode 100644 index 00000000000..98dc58d13a3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_mu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-3.C new file mode 100644 index 00000000000..2c205ef5c5e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_mu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-1.C new file mode 100644 index 00000000000..e37164c9b00 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tu(vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_tu(vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_tu(vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_tu(vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_tu(vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_tu(vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_tu(vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_tu(vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_tu(vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-2.C new file mode 100644 index 00000000000..c0ad6532478 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tu(vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_tu(vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_tu(vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_tu(vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_tu(vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_tu(vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_tu(vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_tu(vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_tu(vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-3.C new file mode 100644 index 00000000000..9534e557bea --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tu(vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_tu(vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_tu(vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_tu(vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_tu(vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_tu(vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_tu(vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_tu(vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_tu(vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-1.C new file mode 100644 index 00000000000..e4cecb10784 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_tum(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-2.C new file mode 100644 index 00000000000..ce6152107ea --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_tum(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-3.C new file mode 100644 index 00000000000..c688e2f0001 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_tum(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C new file mode 100644 index 00000000000..6f462f555bb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_tumu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C new file mode 100644 index 00000000000..87bf15b394f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_tumu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C new file mode 100644 index 00000000000..4c19699db2a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_tumu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */