public inbox for gcc-cvs@sourceware.org help / color / mirror / Atom feed
From: Kito Cheng <kito@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5856] RISC-V: Add vsext C++ API tests Date: Sun, 12 Feb 2023 03:34:03 +0000 (GMT) [thread overview] Message-ID: <20230212033403.705383858017@sourceware.org> (raw) https://gcc.gnu.org/g:74595dd5181813e6cca9464ec7ca04dccf029d4e commit r13-5856-g74595dd5181813e6cca9464ec7ca04dccf029d4e Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Date: Mon Feb 6 13:25:47 2023 +0800 RISC-V: Add vsext C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vsext_vf2-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf2-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf2-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_mu-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_mu-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_mu-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_tu-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_tu-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_tu-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_tum-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_tum-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_tum-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_tumu-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_tumu-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf2_tumu-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf4-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf4-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf4-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_mu-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_mu-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_mu-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_tu-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_tu-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_tu-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_tum-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_tum-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_tum-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_tumu-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_tumu-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf4_tumu-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf8-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf8-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf8-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_mu-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_mu-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_mu-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_tu-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_tu-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_tu-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_tum-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_tum-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_tum-3.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_tumu-1.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_tumu-2.C: New test. * g++.target/riscv/rvv/base/vsext_vf8_tumu-3.C: New test. Diff: --- .../g++.target/riscv/rvv/base/vsext_vf2-1.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2-2.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2-3.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_mu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_mu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_mu-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tu-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tum-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tum-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tum-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tumu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tumu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tumu-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf4-1.C | 132 +++++++++++++ .../g++.target/riscv/rvv/base/vsext_vf4-2.C | 132 +++++++++++++ .../g++.target/riscv/rvv/base/vsext_vf4-3.C | 132 +++++++++++++ .../g++.target/riscv/rvv/base/vsext_vf4_mu-1.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_mu-2.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_mu-3.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_tu-1.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_tu-2.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_tu-3.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_tum-1.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_tum-2.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_tum-3.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_tumu-1.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_tumu-2.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf4_tumu-3.C | 69 +++++++ .../g++.target/riscv/rvv/base/vsext_vf8-1.C | 62 ++++++ .../g++.target/riscv/rvv/base/vsext_vf8-2.C | 62 ++++++ .../g++.target/riscv/rvv/base/vsext_vf8-3.C | 62 ++++++ .../g++.target/riscv/rvv/base/vsext_vf8_mu-1.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_mu-2.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_mu-3.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_tu-1.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_tu-2.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_tu-3.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_tum-1.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_tum-2.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_tum-3.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_tumu-1.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_tumu-2.C | 34 ++++ .../g++.target/riscv/rvv/base/vsext_vf8_tumu-3.C | 34 ++++ 45 files changed, 3798 insertions(+) diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-1.C new file mode 100644 index 00000000000..39d7824fb6f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint16mf2_t test___riscv_vsext_vf2(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint16m1_t test___riscv_vsext_vf2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint16m2_t test___riscv_vsext_vf2(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint16m4_t test___riscv_vsext_vf2(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint16m8_t test___riscv_vsext_vf2(vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint32mf2_t test___riscv_vsext_vf2(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf2(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf2(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf2(vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf2(vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf2(vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf2(vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf2(vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,vl); +} + + +vint16mf4_t test___riscv_vsext_vf2(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint16mf2_t test___riscv_vsext_vf2(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint16m1_t test___riscv_vsext_vf2(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint16m2_t test___riscv_vsext_vf2(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint16m4_t test___riscv_vsext_vf2(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint16m8_t test___riscv_vsext_vf2(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint32mf2_t test___riscv_vsext_vf2(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf2(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf2(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf2(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf2(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf2(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf2(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf2(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf2(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-2.C new file mode 100644 index 00000000000..72e5d06f3d1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint16mf2_t test___riscv_vsext_vf2(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint16m1_t test___riscv_vsext_vf2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint16m2_t test___riscv_vsext_vf2(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint16m4_t test___riscv_vsext_vf2(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint16m8_t test___riscv_vsext_vf2(vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint32mf2_t test___riscv_vsext_vf2(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint32m1_t test___riscv_vsext_vf2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint32m2_t test___riscv_vsext_vf2(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint32m4_t test___riscv_vsext_vf2(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint32m8_t test___riscv_vsext_vf2(vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint64m1_t test___riscv_vsext_vf2(vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint64m2_t test___riscv_vsext_vf2(vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint64m4_t test___riscv_vsext_vf2(vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint64m8_t test___riscv_vsext_vf2(vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,31); +} + + +vint16mf4_t test___riscv_vsext_vf2(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint16mf2_t test___riscv_vsext_vf2(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint16m1_t test___riscv_vsext_vf2(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint16m2_t test___riscv_vsext_vf2(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint16m4_t test___riscv_vsext_vf2(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint16m8_t test___riscv_vsext_vf2(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint32mf2_t test___riscv_vsext_vf2(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf2(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf2(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf2(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf2(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf2(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf2(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf2(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf2(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-3.C new file mode 100644 index 00000000000..3d7ec5ee2a9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint16mf2_t test___riscv_vsext_vf2(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint16m1_t test___riscv_vsext_vf2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint16m2_t test___riscv_vsext_vf2(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint16m4_t test___riscv_vsext_vf2(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint16m8_t test___riscv_vsext_vf2(vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint32mf2_t test___riscv_vsext_vf2(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint32m1_t test___riscv_vsext_vf2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint32m2_t test___riscv_vsext_vf2(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint32m4_t test___riscv_vsext_vf2(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint32m8_t test___riscv_vsext_vf2(vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint64m1_t test___riscv_vsext_vf2(vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint64m2_t test___riscv_vsext_vf2(vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint64m4_t test___riscv_vsext_vf2(vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint64m8_t test___riscv_vsext_vf2(vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(op1,32); +} + + +vint16mf4_t test___riscv_vsext_vf2(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint16mf2_t test___riscv_vsext_vf2(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint16m1_t test___riscv_vsext_vf2(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint16m2_t test___riscv_vsext_vf2(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint16m4_t test___riscv_vsext_vf2(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint16m8_t test___riscv_vsext_vf2(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint32mf2_t test___riscv_vsext_vf2(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf2(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf2(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf2(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf2(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf2(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf2(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf2(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf2(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-1.C new file mode 100644 index 00000000000..5c31d060399 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vsext_vf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vsext_vf2_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vsext_vf2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vsext_vf2_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vsext_vf2_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vsext_vf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf2_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf2_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf2_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf2_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf2_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf2_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-2.C new file mode 100644 index 00000000000..cc4a749d420 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vsext_vf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vsext_vf2_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vsext_vf2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vsext_vf2_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vsext_vf2_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vsext_vf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf2_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf2_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf2_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf2_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf2_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf2_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-3.C new file mode 100644 index 00000000000..c4e6dc950d0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vsext_vf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vsext_vf2_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vsext_vf2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vsext_vf2_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vsext_vf2_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vsext_vf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf2_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf2_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf2_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf2_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf2_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf2_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-1.C new file mode 100644 index 00000000000..dba677e74b8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_tu(vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint16mf2_t test___riscv_vsext_vf2_tu(vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint16m1_t test___riscv_vsext_vf2_tu(vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint16m2_t test___riscv_vsext_vf2_tu(vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint16m4_t test___riscv_vsext_vf2_tu(vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint16m8_t test___riscv_vsext_vf2_tu(vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint32mf2_t test___riscv_vsext_vf2_tu(vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf2_tu(vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf2_tu(vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf2_tu(vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf2_tu(vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf2_tu(vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf2_tu(vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf2_tu(vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf2_tu(vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-2.C new file mode 100644 index 00000000000..b2f71e22d1b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_tu(vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint16mf2_t test___riscv_vsext_vf2_tu(vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint16m1_t test___riscv_vsext_vf2_tu(vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint16m2_t test___riscv_vsext_vf2_tu(vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint16m4_t test___riscv_vsext_vf2_tu(vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint16m8_t test___riscv_vsext_vf2_tu(vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint32mf2_t test___riscv_vsext_vf2_tu(vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf2_tu(vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf2_tu(vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf2_tu(vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf2_tu(vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf2_tu(vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf2_tu(vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf2_tu(vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf2_tu(vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-3.C new file mode 100644 index 00000000000..4af72f294e0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_tu(vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint16mf2_t test___riscv_vsext_vf2_tu(vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint16m1_t test___riscv_vsext_vf2_tu(vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint16m2_t test___riscv_vsext_vf2_tu(vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint16m4_t test___riscv_vsext_vf2_tu(vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint16m8_t test___riscv_vsext_vf2_tu(vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint32mf2_t test___riscv_vsext_vf2_tu(vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf2_tu(vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf2_tu(vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf2_tu(vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf2_tu(vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf2_tu(vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf2_tu(vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf2_tu(vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf2_tu(vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-1.C new file mode 100644 index 00000000000..e6369028b1c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vsext_vf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vsext_vf2_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vsext_vf2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vsext_vf2_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vsext_vf2_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vsext_vf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf2_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf2_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf2_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf2_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf2_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf2_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-2.C new file mode 100644 index 00000000000..dadcd57fc11 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vsext_vf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vsext_vf2_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vsext_vf2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vsext_vf2_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vsext_vf2_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vsext_vf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf2_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf2_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf2_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf2_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf2_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf2_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-3.C new file mode 100644 index 00000000000..fa992a15dbb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vsext_vf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vsext_vf2_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vsext_vf2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vsext_vf2_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vsext_vf2_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vsext_vf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf2_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf2_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf2_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf2_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf2_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf2_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-1.C new file mode 100644 index 00000000000..857360f00bc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vsext_vf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vsext_vf2_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vsext_vf2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vsext_vf2_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vsext_vf2_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vsext_vf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf2_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf2_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf2_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf2_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf2_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf2_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-2.C new file mode 100644 index 00000000000..77c049a8968 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vsext_vf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vsext_vf2_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vsext_vf2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vsext_vf2_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vsext_vf2_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vsext_vf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf2_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf2_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf2_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf2_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf2_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf2_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-3.C new file mode 100644 index 00000000000..bb93483b971 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vsext_vf2_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vsext_vf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vsext_vf2_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vsext_vf2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vsext_vf2_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vsext_vf2_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vsext_vf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf2_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf2_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf2_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf2_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf2_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf2_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vsext_vf2_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-1.C new file mode 100644 index 00000000000..4c7bd607bbb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-1.C @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,vl); +} + + +vint32mf2_t test___riscv_vsext_vf4(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-2.C new file mode 100644 index 00000000000..872d8b7a11d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-2.C @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,31); +} + + +vint32mf2_t test___riscv_vsext_vf4(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-3.C new file mode 100644 index 00000000000..a51438a54cc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-3.C @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(op1,32); +} + + +vint32mf2_t test___riscv_vsext_vf4(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-1.C new file mode 100644 index 00000000000..7297b0c4548 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_mu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_mu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_mu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_mu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_mu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_mu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_mu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_mu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_mu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-2.C new file mode 100644 index 00000000000..8ad4b1deb06 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_mu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_mu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_mu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_mu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_mu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_mu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_mu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_mu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_mu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-3.C new file mode 100644 index 00000000000..e773403a3d0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_mu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_mu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_mu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_mu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_mu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_mu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_mu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_mu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_mu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-1.C new file mode 100644 index 00000000000..ac651986404 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_tu(vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_tu(vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_tu(vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_tu(vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_tu(vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_tu(vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_tu(vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_tu(vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_tu(vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-2.C new file mode 100644 index 00000000000..32f3c58c683 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_tu(vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_tu(vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_tu(vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_tu(vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_tu(vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_tu(vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_tu(vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_tu(vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_tu(vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-3.C new file mode 100644 index 00000000000..bb93b8085e9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_tu(vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_tu(vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_tu(vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_tu(vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_tu(vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_tu(vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_tu(vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_tu(vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_tu(vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-1.C new file mode 100644 index 00000000000..0ff0a3789a9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_tum(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_tum(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_tum(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_tum(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_tum(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_tum(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_tum(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_tum(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_tum(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-2.C new file mode 100644 index 00000000000..60ddee57161 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_tum(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_tum(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_tum(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_tum(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_tum(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_tum(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_tum(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_tum(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_tum(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-3.C new file mode 100644 index 00000000000..23dc1f65c53 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_tum(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_tum(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_tum(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_tum(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_tum(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_tum(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_tum(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_tum(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_tum(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-1.C new file mode 100644 index 00000000000..72641da20ac --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_tumu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_tumu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_tumu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_tumu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_tumu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_tumu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_tumu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_tumu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_tumu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-2.C new file mode 100644 index 00000000000..80a093bf9e5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_tumu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_tumu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_tumu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_tumu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_tumu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_tumu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_tumu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_tumu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_tumu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-3.C new file mode 100644 index 00000000000..6ac4e9d1fc5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_tumu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_tumu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_tumu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_tumu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_tumu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_tumu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_tumu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_tumu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_tumu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-1.C new file mode 100644 index 00000000000..823c00af68f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-1.C @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf8(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-2.C new file mode 100644 index 00000000000..349e8b6794d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-2.C @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,31); +} + + +vint64m1_t test___riscv_vsext_vf8(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-3.C new file mode 100644 index 00000000000..3c52c429d98 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-3.C @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8(op1,32); +} + + +vint64m1_t test___riscv_vsext_vf8(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-1.C new file mode 100644 index 00000000000..b39dfd2adab --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-1.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_mu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_mu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_mu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_mu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-2.C new file mode 100644 index 00000000000..9009dfe1c15 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-2.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_mu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_mu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_mu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_mu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-3.C new file mode 100644 index 00000000000..2e9e930a45e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-3.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_mu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_mu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_mu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_mu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-1.C new file mode 100644 index 00000000000..8728e6b6e66 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-1.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_tu(vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_tu(vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_tu(vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_tu(vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-2.C new file mode 100644 index 00000000000..887293f78b1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-2.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_tu(vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_tu(vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_tu(vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_tu(vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-3.C new file mode 100644 index 00000000000..6191e8b0fe6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-3.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_tu(vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_tu(vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_tu(vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_tu(vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-1.C new file mode 100644 index 00000000000..7437331c3cd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-1.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_tum(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_tum(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_tum(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_tum(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-2.C new file mode 100644 index 00000000000..32d7f548a30 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-2.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_tum(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_tum(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_tum(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_tum(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-3.C new file mode 100644 index 00000000000..e07af599135 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-3.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_tum(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_tum(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_tum(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_tum(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-1.C new file mode 100644 index 00000000000..d7ad1da7e4f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-1.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_tumu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_tumu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_tumu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_tumu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-2.C new file mode 100644 index 00000000000..45321a48852 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-2.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_tumu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_tumu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_tumu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_tumu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-3.C new file mode 100644 index 00000000000..8cbee9e614d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-3.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_tumu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_tumu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_tumu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_tumu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
reply other threads:[~2023-02-12 3:34 UTC|newest] Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230212033403.705383858017@sourceware.org \ --to=kito@gcc.gnu.org \ --cc=gcc-cvs@gcc.gnu.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).