From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id C6C44385841A; Sun, 12 Feb 2023 07:35:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C6C44385841A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676187305; bh=3shqq0SADIoBlXvOATgqZA4KAVOOXskolS75XKXbjxM=; h=From:To:Subject:Date:From; b=dgM5B5aBbZuBUfhzuucv9PnaJ/1TKlDpSHZbiLSeq0DVqACmqmcTLVOW93v7eojp/ sYOddxmWyHR23pWzhLJNtvw1if5TqCwSEpV0268hrIrf1qYGmzIfXN8Jt8VdiE7uCc I7irXKENgAeNRLzgzPL+aYu7Ub/3xbAUxetXux9I= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-5915] RISC-V: Add vmv.v.x C API tests X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: c1294253310014627d4294ae67eafef10c4c77e2 X-Git-Newrev: 4852c719a1adccf9f6b41d5cb2b542f579b9c06f Message-Id: <20230212073505.C6C44385841A@sourceware.org> Date: Sun, 12 Feb 2023 07:35:05 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4852c719a1adccf9f6b41d5cb2b542f579b9c06f commit r13-5915-g4852c719a1adccf9f6b41d5cb2b542f579b9c06f Author: Ju-Zhe Zhong Date: Fri Feb 10 05:56:12 2023 +0800 RISC-V: Add vmv.v.x C API tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c: New test. Diff: --- .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c | 289 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c | 289 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c | 289 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c | 292 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c | 292 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c | 292 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c | 289 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c | 289 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c | 289 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c | 292 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c | 292 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c | 292 +++++++++++++++++++++ 12 files changed, 3486 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c new file mode 100644 index 00000000000..96f490ee5d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8(src,vl); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4(src,vl); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2(src,vl); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1(src,vl); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2(src,vl); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4(src,vl); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8(src,vl); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4(src,vl); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2(src,vl); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1(src,vl); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2(src,vl); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4(src,vl); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8(src,vl); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2(src,vl); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1(src,vl); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2(src,vl); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4(src,vl); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8(src,vl); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1(src,vl); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2(src,vl); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4(src,vl); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8(src,vl); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8(src,vl); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4(src,vl); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2(src,vl); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1(src,vl); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2(src,vl); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4(src,vl); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8(src,vl); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4(src,vl); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2(src,vl); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1(src,vl); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2(src,vl); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4(src,vl); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8(src,vl); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2(src,vl); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1(src,vl); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2(src,vl); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4(src,vl); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8(src,vl); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1(src,vl); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2(src,vl); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4(src,vl); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8(src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vlse} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c new file mode 100644 index 00000000000..c34d710b250 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8(src,31); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4(src,31); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2(src,31); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1(src,31); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2(src,31); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4(src,31); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8(src,31); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4(src,31); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2(src,31); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1(src,31); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2(src,31); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4(src,31); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8(src,31); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2(src,31); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1(src,31); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2(src,31); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4(src,31); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8(src,31); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1(src,31); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2(src,31); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4(src,31); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8(src,31); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8(src,31); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4(src,31); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2(src,31); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1(src,31); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2(src,31); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4(src,31); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8(src,31); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4(src,31); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2(src,31); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1(src,31); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2(src,31); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4(src,31); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8(src,31); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2(src,31); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1(src,31); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2(src,31); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4(src,31); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8(src,31); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1(src,31); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2(src,31); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4(src,31); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8(src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vlse} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c new file mode 100644 index 00000000000..8332d299736 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8(src,32); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4(src,32); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2(src,32); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1(src,32); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2(src,32); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4(src,32); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8(src,32); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4(src,32); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2(src,32); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1(src,32); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2(src,32); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4(src,32); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8(src,32); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2(src,32); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1(src,32); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2(src,32); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4(src,32); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8(src,32); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1(src,32); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2(src,32); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4(src,32); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8(src,32); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8(src,32); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4(src,32); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2(src,32); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1(src,32); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2(src,32); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4(src,32); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8(src,32); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4(src,32); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2(src,32); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1(src,32); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2(src,32); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4(src,32); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8(src,32); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2(src,32); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1(src,32); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2(src,32); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4(src,32); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8(src,32); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1(src,32); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2(src,32); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4(src,32); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8(src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vlse} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c new file mode 100644 index 00000000000..91278068c8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8(src,vl); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4(src,vl); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2(src,vl); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1(src,vl); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2(src,vl); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4(src,vl); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8(src,vl); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4(src,vl); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2(src,vl); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1(src,vl); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2(src,vl); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4(src,vl); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8(src,vl); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2(src,vl); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1(src,vl); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2(src,vl); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4(src,vl); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8(src,vl); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1(src,vl); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2(src,vl); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4(src,vl); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8(src,vl); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8(src,vl); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4(src,vl); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2(src,vl); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1(src,vl); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2(src,vl); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4(src,vl); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8(src,vl); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4(src,vl); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2(src,vl); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1(src,vl); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2(src,vl); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4(src,vl); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8(src,vl); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2(src,vl); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1(src,vl); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2(src,vl); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4(src,vl); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8(src,vl); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1(src,vl); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2(src,vl); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4(src,vl); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8(src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c new file mode 100644 index 00000000000..68a8886a6e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8(src,31); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4(src,31); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2(src,31); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1(src,31); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2(src,31); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4(src,31); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8(src,31); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4(src,31); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2(src,31); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1(src,31); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2(src,31); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4(src,31); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8(src,31); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2(src,31); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1(src,31); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2(src,31); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4(src,31); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8(src,31); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1(src,31); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2(src,31); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4(src,31); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8(src,31); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8(src,31); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4(src,31); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2(src,31); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1(src,31); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2(src,31); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4(src,31); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8(src,31); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4(src,31); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2(src,31); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1(src,31); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2(src,31); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4(src,31); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8(src,31); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2(src,31); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1(src,31); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2(src,31); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4(src,31); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8(src,31); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1(src,31); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2(src,31); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4(src,31); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8(src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c new file mode 100644 index 00000000000..c8aea77cf6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8(src,32); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4(src,32); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2(src,32); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1(src,32); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2(src,32); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4(src,32); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8(src,32); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4(src,32); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2(src,32); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1(src,32); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2(src,32); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4(src,32); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8(src,32); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2(src,32); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1(src,32); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2(src,32); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4(src,32); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8(src,32); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1(src,32); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2(src,32); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4(src,32); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8(src,32); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8(src,32); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4(src,32); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2(src,32); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1(src,32); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2(src,32); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4(src,32); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8(src,32); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4(src,32); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2(src,32); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1(src,32); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2(src,32); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4(src,32); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8(src,32); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2(src,32); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1(src,32); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2(src,32); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4(src,32); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8(src,32); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1(src,32); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2(src,32); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4(src,32); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8(src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c new file mode 100644 index 00000000000..66fbc3b6002 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8_tu(vint8mf8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8_tu(merge,src,vl); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4_tu(vint8mf4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4_tu(merge,src,vl); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2_tu(vint8mf2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2_tu(merge,src,vl); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1_tu(vint8m1_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1_tu(merge,src,vl); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2_tu(vint8m2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2_tu(merge,src,vl); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4_tu(vint8m4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4_tu(merge,src,vl); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8_tu(vint8m8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8_tu(merge,src,vl); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4_tu(vint16mf4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4_tu(merge,src,vl); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2_tu(vint16mf2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2_tu(merge,src,vl); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1_tu(vint16m1_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1_tu(merge,src,vl); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2_tu(vint16m2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2_tu(merge,src,vl); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4_tu(vint16m4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4_tu(merge,src,vl); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8_tu(vint16m8_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8_tu(merge,src,vl); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2_tu(vint32mf2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2_tu(merge,src,vl); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1_tu(vint32m1_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1_tu(merge,src,vl); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2_tu(vint32m2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2_tu(merge,src,vl); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4_tu(vint32m4_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4_tu(merge,src,vl); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8_tu(vint32m8_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8_tu(merge,src,vl); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1_tu(vint64m1_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1_tu(merge,src,vl); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2_tu(vint64m2_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2_tu(merge,src,vl); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4_tu(vint64m4_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4_tu(merge,src,vl); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8_tu(vint64m8_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8_tu(merge,src,vl); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8_tu(vuint8mf8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8_tu(merge,src,vl); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4_tu(vuint8mf4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4_tu(merge,src,vl); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2_tu(vuint8mf2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2_tu(merge,src,vl); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1_tu(vuint8m1_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1_tu(merge,src,vl); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2_tu(vuint8m2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2_tu(merge,src,vl); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4_tu(vuint8m4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4_tu(merge,src,vl); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8_tu(vuint8m8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8_tu(merge,src,vl); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4_tu(vuint16mf4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4_tu(merge,src,vl); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2_tu(vuint16mf2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2_tu(merge,src,vl); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1_tu(vuint16m1_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1_tu(merge,src,vl); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2_tu(vuint16m2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2_tu(merge,src,vl); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4_tu(vuint16m4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4_tu(merge,src,vl); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8_tu(vuint16m8_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8_tu(merge,src,vl); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2_tu(vuint32mf2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2_tu(merge,src,vl); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1_tu(vuint32m1_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1_tu(merge,src,vl); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2_tu(vuint32m2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2_tu(merge,src,vl); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4_tu(vuint32m4_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4_tu(merge,src,vl); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8_tu(vuint32m8_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8_tu(merge,src,vl); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1_tu(vuint64m1_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1_tu(merge,src,vl); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2_tu(vuint64m2_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2_tu(merge,src,vl); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4_tu(vuint64m4_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4_tu(merge,src,vl); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8_tu(vuint64m8_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8_tu(merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vlse} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c new file mode 100644 index 00000000000..5b20bd1d6e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8_tu(vint8mf8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8_tu(merge,src,31); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4_tu(vint8mf4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4_tu(merge,src,31); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2_tu(vint8mf2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2_tu(merge,src,31); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1_tu(vint8m1_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1_tu(merge,src,31); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2_tu(vint8m2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2_tu(merge,src,31); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4_tu(vint8m4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4_tu(merge,src,31); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8_tu(vint8m8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8_tu(merge,src,31); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4_tu(vint16mf4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4_tu(merge,src,31); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2_tu(vint16mf2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2_tu(merge,src,31); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1_tu(vint16m1_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1_tu(merge,src,31); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2_tu(vint16m2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2_tu(merge,src,31); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4_tu(vint16m4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4_tu(merge,src,31); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8_tu(vint16m8_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8_tu(merge,src,31); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2_tu(vint32mf2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2_tu(merge,src,31); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1_tu(vint32m1_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1_tu(merge,src,31); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2_tu(vint32m2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2_tu(merge,src,31); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4_tu(vint32m4_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4_tu(merge,src,31); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8_tu(vint32m8_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8_tu(merge,src,31); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1_tu(vint64m1_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1_tu(merge,src,31); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2_tu(vint64m2_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2_tu(merge,src,31); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4_tu(vint64m4_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4_tu(merge,src,31); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8_tu(vint64m8_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8_tu(merge,src,31); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8_tu(vuint8mf8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8_tu(merge,src,31); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4_tu(vuint8mf4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4_tu(merge,src,31); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2_tu(vuint8mf2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2_tu(merge,src,31); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1_tu(vuint8m1_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1_tu(merge,src,31); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2_tu(vuint8m2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2_tu(merge,src,31); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4_tu(vuint8m4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4_tu(merge,src,31); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8_tu(vuint8m8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8_tu(merge,src,31); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4_tu(vuint16mf4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4_tu(merge,src,31); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2_tu(vuint16mf2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2_tu(merge,src,31); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1_tu(vuint16m1_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1_tu(merge,src,31); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2_tu(vuint16m2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2_tu(merge,src,31); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4_tu(vuint16m4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4_tu(merge,src,31); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8_tu(vuint16m8_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8_tu(merge,src,31); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2_tu(vuint32mf2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2_tu(merge,src,31); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1_tu(vuint32m1_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1_tu(merge,src,31); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2_tu(vuint32m2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2_tu(merge,src,31); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4_tu(vuint32m4_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4_tu(merge,src,31); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8_tu(vuint32m8_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8_tu(merge,src,31); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1_tu(vuint64m1_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1_tu(merge,src,31); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2_tu(vuint64m2_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2_tu(merge,src,31); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4_tu(vuint64m4_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4_tu(merge,src,31); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8_tu(vuint64m8_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8_tu(merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vlse} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c new file mode 100644 index 00000000000..32a2bd50dd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8_tu(vint8mf8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8_tu(merge,src,32); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4_tu(vint8mf4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4_tu(merge,src,32); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2_tu(vint8mf2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2_tu(merge,src,32); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1_tu(vint8m1_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1_tu(merge,src,32); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2_tu(vint8m2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2_tu(merge,src,32); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4_tu(vint8m4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4_tu(merge,src,32); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8_tu(vint8m8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8_tu(merge,src,32); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4_tu(vint16mf4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4_tu(merge,src,32); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2_tu(vint16mf2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2_tu(merge,src,32); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1_tu(vint16m1_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1_tu(merge,src,32); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2_tu(vint16m2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2_tu(merge,src,32); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4_tu(vint16m4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4_tu(merge,src,32); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8_tu(vint16m8_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8_tu(merge,src,32); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2_tu(vint32mf2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2_tu(merge,src,32); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1_tu(vint32m1_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1_tu(merge,src,32); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2_tu(vint32m2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2_tu(merge,src,32); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4_tu(vint32m4_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4_tu(merge,src,32); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8_tu(vint32m8_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8_tu(merge,src,32); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1_tu(vint64m1_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1_tu(merge,src,32); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2_tu(vint64m2_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2_tu(merge,src,32); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4_tu(vint64m4_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4_tu(merge,src,32); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8_tu(vint64m8_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8_tu(merge,src,32); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8_tu(vuint8mf8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8_tu(merge,src,32); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4_tu(vuint8mf4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4_tu(merge,src,32); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2_tu(vuint8mf2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2_tu(merge,src,32); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1_tu(vuint8m1_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1_tu(merge,src,32); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2_tu(vuint8m2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2_tu(merge,src,32); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4_tu(vuint8m4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4_tu(merge,src,32); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8_tu(vuint8m8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8_tu(merge,src,32); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4_tu(vuint16mf4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4_tu(merge,src,32); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2_tu(vuint16mf2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2_tu(merge,src,32); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1_tu(vuint16m1_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1_tu(merge,src,32); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2_tu(vuint16m2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2_tu(merge,src,32); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4_tu(vuint16m4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4_tu(merge,src,32); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8_tu(vuint16m8_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8_tu(merge,src,32); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2_tu(vuint32mf2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2_tu(merge,src,32); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1_tu(vuint32m1_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1_tu(merge,src,32); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2_tu(vuint32m2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2_tu(merge,src,32); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4_tu(vuint32m4_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4_tu(merge,src,32); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8_tu(vuint32m8_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8_tu(merge,src,32); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1_tu(vuint64m1_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1_tu(merge,src,32); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2_tu(vuint64m2_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2_tu(merge,src,32); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4_tu(vuint64m4_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4_tu(merge,src,32); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8_tu(vuint64m8_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8_tu(merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vlse} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c new file mode 100644 index 00000000000..b0959b19f85 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8_tu(vint8mf8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8_tu(merge,src,vl); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4_tu(vint8mf4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4_tu(merge,src,vl); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2_tu(vint8mf2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2_tu(merge,src,vl); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1_tu(vint8m1_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1_tu(merge,src,vl); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2_tu(vint8m2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2_tu(merge,src,vl); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4_tu(vint8m4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4_tu(merge,src,vl); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8_tu(vint8m8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8_tu(merge,src,vl); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4_tu(vint16mf4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4_tu(merge,src,vl); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2_tu(vint16mf2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2_tu(merge,src,vl); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1_tu(vint16m1_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1_tu(merge,src,vl); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2_tu(vint16m2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2_tu(merge,src,vl); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4_tu(vint16m4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4_tu(merge,src,vl); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8_tu(vint16m8_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8_tu(merge,src,vl); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2_tu(vint32mf2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2_tu(merge,src,vl); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1_tu(vint32m1_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1_tu(merge,src,vl); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2_tu(vint32m2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2_tu(merge,src,vl); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4_tu(vint32m4_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4_tu(merge,src,vl); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8_tu(vint32m8_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8_tu(merge,src,vl); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1_tu(vint64m1_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1_tu(merge,src,vl); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2_tu(vint64m2_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2_tu(merge,src,vl); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4_tu(vint64m4_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4_tu(merge,src,vl); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8_tu(vint64m8_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8_tu(merge,src,vl); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8_tu(vuint8mf8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8_tu(merge,src,vl); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4_tu(vuint8mf4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4_tu(merge,src,vl); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2_tu(vuint8mf2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2_tu(merge,src,vl); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1_tu(vuint8m1_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1_tu(merge,src,vl); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2_tu(vuint8m2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2_tu(merge,src,vl); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4_tu(vuint8m4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4_tu(merge,src,vl); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8_tu(vuint8m8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8_tu(merge,src,vl); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4_tu(vuint16mf4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4_tu(merge,src,vl); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2_tu(vuint16mf2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2_tu(merge,src,vl); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1_tu(vuint16m1_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1_tu(merge,src,vl); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2_tu(vuint16m2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2_tu(merge,src,vl); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4_tu(vuint16m4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4_tu(merge,src,vl); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8_tu(vuint16m8_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8_tu(merge,src,vl); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2_tu(vuint32mf2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2_tu(merge,src,vl); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1_tu(vuint32m1_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1_tu(merge,src,vl); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2_tu(vuint32m2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2_tu(merge,src,vl); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4_tu(vuint32m4_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4_tu(merge,src,vl); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8_tu(vuint32m8_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8_tu(merge,src,vl); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1_tu(vuint64m1_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1_tu(merge,src,vl); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2_tu(vuint64m2_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2_tu(merge,src,vl); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4_tu(vuint64m4_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4_tu(merge,src,vl); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8_tu(vuint64m8_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8_tu(merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c new file mode 100644 index 00000000000..9d42f244360 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8_tu(vint8mf8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8_tu(merge,src,31); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4_tu(vint8mf4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4_tu(merge,src,31); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2_tu(vint8mf2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2_tu(merge,src,31); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1_tu(vint8m1_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1_tu(merge,src,31); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2_tu(vint8m2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2_tu(merge,src,31); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4_tu(vint8m4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4_tu(merge,src,31); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8_tu(vint8m8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8_tu(merge,src,31); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4_tu(vint16mf4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4_tu(merge,src,31); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2_tu(vint16mf2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2_tu(merge,src,31); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1_tu(vint16m1_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1_tu(merge,src,31); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2_tu(vint16m2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2_tu(merge,src,31); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4_tu(vint16m4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4_tu(merge,src,31); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8_tu(vint16m8_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8_tu(merge,src,31); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2_tu(vint32mf2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2_tu(merge,src,31); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1_tu(vint32m1_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1_tu(merge,src,31); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2_tu(vint32m2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2_tu(merge,src,31); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4_tu(vint32m4_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4_tu(merge,src,31); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8_tu(vint32m8_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8_tu(merge,src,31); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1_tu(vint64m1_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1_tu(merge,src,31); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2_tu(vint64m2_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2_tu(merge,src,31); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4_tu(vint64m4_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4_tu(merge,src,31); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8_tu(vint64m8_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8_tu(merge,src,31); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8_tu(vuint8mf8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8_tu(merge,src,31); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4_tu(vuint8mf4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4_tu(merge,src,31); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2_tu(vuint8mf2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2_tu(merge,src,31); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1_tu(vuint8m1_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1_tu(merge,src,31); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2_tu(vuint8m2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2_tu(merge,src,31); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4_tu(vuint8m4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4_tu(merge,src,31); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8_tu(vuint8m8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8_tu(merge,src,31); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4_tu(vuint16mf4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4_tu(merge,src,31); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2_tu(vuint16mf2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2_tu(merge,src,31); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1_tu(vuint16m1_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1_tu(merge,src,31); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2_tu(vuint16m2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2_tu(merge,src,31); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4_tu(vuint16m4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4_tu(merge,src,31); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8_tu(vuint16m8_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8_tu(merge,src,31); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2_tu(vuint32mf2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2_tu(merge,src,31); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1_tu(vuint32m1_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1_tu(merge,src,31); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2_tu(vuint32m2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2_tu(merge,src,31); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4_tu(vuint32m4_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4_tu(merge,src,31); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8_tu(vuint32m8_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8_tu(merge,src,31); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1_tu(vuint64m1_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1_tu(merge,src,31); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2_tu(vuint64m2_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2_tu(merge,src,31); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4_tu(vuint64m4_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4_tu(merge,src,31); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8_tu(vuint64m8_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8_tu(merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c new file mode 100644 index 00000000000..fc240d6caaf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_x_i8mf8_tu(vint8mf8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf8_tu(merge,src,32); +} + + +vint8mf4_t test___riscv_vmv_v_x_i8mf4_tu(vint8mf4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf4_tu(merge,src,32); +} + + +vint8mf2_t test___riscv_vmv_v_x_i8mf2_tu(vint8mf2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8mf2_tu(merge,src,32); +} + + +vint8m1_t test___riscv_vmv_v_x_i8m1_tu(vint8m1_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m1_tu(merge,src,32); +} + + +vint8m2_t test___riscv_vmv_v_x_i8m2_tu(vint8m2_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m2_tu(merge,src,32); +} + + +vint8m4_t test___riscv_vmv_v_x_i8m4_tu(vint8m4_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m4_tu(merge,src,32); +} + + +vint8m8_t test___riscv_vmv_v_x_i8m8_tu(vint8m8_t merge,int8_t src,size_t vl) +{ + return __riscv_vmv_v_x_i8m8_tu(merge,src,32); +} + + +vint16mf4_t test___riscv_vmv_v_x_i16mf4_tu(vint16mf4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf4_tu(merge,src,32); +} + + +vint16mf2_t test___riscv_vmv_v_x_i16mf2_tu(vint16mf2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16mf2_tu(merge,src,32); +} + + +vint16m1_t test___riscv_vmv_v_x_i16m1_tu(vint16m1_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m1_tu(merge,src,32); +} + + +vint16m2_t test___riscv_vmv_v_x_i16m2_tu(vint16m2_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m2_tu(merge,src,32); +} + + +vint16m4_t test___riscv_vmv_v_x_i16m4_tu(vint16m4_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m4_tu(merge,src,32); +} + + +vint16m8_t test___riscv_vmv_v_x_i16m8_tu(vint16m8_t merge,int16_t src,size_t vl) +{ + return __riscv_vmv_v_x_i16m8_tu(merge,src,32); +} + + +vint32mf2_t test___riscv_vmv_v_x_i32mf2_tu(vint32mf2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32mf2_tu(merge,src,32); +} + + +vint32m1_t test___riscv_vmv_v_x_i32m1_tu(vint32m1_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m1_tu(merge,src,32); +} + + +vint32m2_t test___riscv_vmv_v_x_i32m2_tu(vint32m2_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m2_tu(merge,src,32); +} + + +vint32m4_t test___riscv_vmv_v_x_i32m4_tu(vint32m4_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m4_tu(merge,src,32); +} + + +vint32m8_t test___riscv_vmv_v_x_i32m8_tu(vint32m8_t merge,int32_t src,size_t vl) +{ + return __riscv_vmv_v_x_i32m8_tu(merge,src,32); +} + + +vint64m1_t test___riscv_vmv_v_x_i64m1_tu(vint64m1_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m1_tu(merge,src,32); +} + + +vint64m2_t test___riscv_vmv_v_x_i64m2_tu(vint64m2_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m2_tu(merge,src,32); +} + + +vint64m4_t test___riscv_vmv_v_x_i64m4_tu(vint64m4_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m4_tu(merge,src,32); +} + + +vint64m8_t test___riscv_vmv_v_x_i64m8_tu(vint64m8_t merge,int64_t src,size_t vl) +{ + return __riscv_vmv_v_x_i64m8_tu(merge,src,32); +} + + +vuint8mf8_t test___riscv_vmv_v_x_u8mf8_tu(vuint8mf8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf8_tu(merge,src,32); +} + + +vuint8mf4_t test___riscv_vmv_v_x_u8mf4_tu(vuint8mf4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf4_tu(merge,src,32); +} + + +vuint8mf2_t test___riscv_vmv_v_x_u8mf2_tu(vuint8mf2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8mf2_tu(merge,src,32); +} + + +vuint8m1_t test___riscv_vmv_v_x_u8m1_tu(vuint8m1_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m1_tu(merge,src,32); +} + + +vuint8m2_t test___riscv_vmv_v_x_u8m2_tu(vuint8m2_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m2_tu(merge,src,32); +} + + +vuint8m4_t test___riscv_vmv_v_x_u8m4_tu(vuint8m4_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m4_tu(merge,src,32); +} + + +vuint8m8_t test___riscv_vmv_v_x_u8m8_tu(vuint8m8_t merge,uint8_t src,size_t vl) +{ + return __riscv_vmv_v_x_u8m8_tu(merge,src,32); +} + + +vuint16mf4_t test___riscv_vmv_v_x_u16mf4_tu(vuint16mf4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf4_tu(merge,src,32); +} + + +vuint16mf2_t test___riscv_vmv_v_x_u16mf2_tu(vuint16mf2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16mf2_tu(merge,src,32); +} + + +vuint16m1_t test___riscv_vmv_v_x_u16m1_tu(vuint16m1_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m1_tu(merge,src,32); +} + + +vuint16m2_t test___riscv_vmv_v_x_u16m2_tu(vuint16m2_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m2_tu(merge,src,32); +} + + +vuint16m4_t test___riscv_vmv_v_x_u16m4_tu(vuint16m4_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m4_tu(merge,src,32); +} + + +vuint16m8_t test___riscv_vmv_v_x_u16m8_tu(vuint16m8_t merge,uint16_t src,size_t vl) +{ + return __riscv_vmv_v_x_u16m8_tu(merge,src,32); +} + + +vuint32mf2_t test___riscv_vmv_v_x_u32mf2_tu(vuint32mf2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32mf2_tu(merge,src,32); +} + + +vuint32m1_t test___riscv_vmv_v_x_u32m1_tu(vuint32m1_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m1_tu(merge,src,32); +} + + +vuint32m2_t test___riscv_vmv_v_x_u32m2_tu(vuint32m2_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m2_tu(merge,src,32); +} + + +vuint32m4_t test___riscv_vmv_v_x_u32m4_tu(vuint32m4_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m4_tu(merge,src,32); +} + + +vuint32m8_t test___riscv_vmv_v_x_u32m8_tu(vuint32m8_t merge,uint32_t src,size_t vl) +{ + return __riscv_vmv_v_x_u32m8_tu(merge,src,32); +} + + +vuint64m1_t test___riscv_vmv_v_x_u64m1_tu(vuint64m1_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m1_tu(merge,src,32); +} + + +vuint64m2_t test___riscv_vmv_v_x_u64m2_tu(vuint64m2_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m2_tu(merge,src,32); +} + + +vuint64m4_t test___riscv_vmv_v_x_u64m4_tu(vuint64m4_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m4_tu(merge,src,32); +} + + +vuint64m8_t test___riscv_vmv_v_x_u64m8_tu(vuint64m8_t merge,uint64_t src,size_t vl) +{ + return __riscv_vmv_v_x_u64m8_tu(merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 2 } } */