From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id C42893858000; Wed, 15 Feb 2023 13:30:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C42893858000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676467844; bh=EMDOHyE33mzEGQsk60v6m08NVmeRUX2IyHW6J6PYOOk=; h=From:To:Subject:Date:From; b=oTbmKykaeyW+FKjEMiS4hdvFkfwF9lrNtB+8zt3uVFFOoACeuYmbC+vFQdQaZSIQN dzAHXC5WfiRWlf8S0YoXaSbB0kelTua6VfNfgz1ktGG4xJ+sxI1RIJ/Nmed/6L3p4a xMkaOZywXMJ9cTTxECI4fbakJmH6O2Os6RA0skq0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-6018] RISC-V: Add binop constraints tests for integer compare X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 4d06fc379093fd2353c6e09619d40bc15c89465a X-Git-Newrev: 6ec7b7b3e46da49ce9e9fb38e1c1405f988d76ae Message-Id: <20230215133044.C42893858000@sourceware.org> Date: Wed, 15 Feb 2023 13:30:44 +0000 (GMT) List-Id: https://gcc.gnu.org/g:6ec7b7b3e46da49ce9e9fb38e1c1405f988d76ae commit r13-6018-g6ec7b7b3e46da49ce9e9fb38e1c1405f988d76ae Author: Ju-Zhe Zhong Date: Mon Feb 13 16:25:22 2023 +0800 RISC-V: Add binop constraints tests for integer compare gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vv_constraint-2.c: New test. * gcc.target/riscv/rvv/base/binop_vv_constraint-3.c: New test. * gcc.target/riscv/rvv/base/binop_vv_constraint-4.c: New test. * gcc.target/riscv/rvv/base/binop_vv_constraint-5.c: New test. * gcc.target/riscv/rvv/base/binop_vv_constraint-6.c: New test. * gcc.target/riscv/rvv/base/binop_vv_constraint-7.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-123.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-124.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-125.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-126.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-127.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-128.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-129.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-130.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-131.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-132.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-133.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-134.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-135.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-136.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-137.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-138.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-139.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-140.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-141.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-142.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-143.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-144.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-145.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-146.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-147.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-148.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-149.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-150.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-151.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-152.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-153.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-154.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-155.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-156.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-157.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-158.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-159.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-160.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-161.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-162.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-163.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-164.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-165.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-166.c: New test. Diff: --- .../riscv/rvv/base/binop_vv_constraint-2.c | 15 +++ .../riscv/rvv/base/binop_vv_constraint-3.c | 27 +++++ .../riscv/rvv/base/binop_vv_constraint-4.c | 27 +++++ .../riscv/rvv/base/binop_vv_constraint-5.c | 29 +++++ .../riscv/rvv/base/binop_vv_constraint-6.c | 27 +++++ .../riscv/rvv/base/binop_vv_constraint-7.c | 29 +++++ .../riscv/rvv/base/binop_vx_constraint-123.c | 15 +++ .../riscv/rvv/base/binop_vx_constraint-124.c | 27 +++++ .../riscv/rvv/base/binop_vx_constraint-125.c | 27 +++++ .../riscv/rvv/base/binop_vx_constraint-126.c | 29 +++++ .../riscv/rvv/base/binop_vx_constraint-127.c | 27 +++++ .../riscv/rvv/base/binop_vx_constraint-128.c | 29 +++++ .../riscv/rvv/base/binop_vx_constraint-129.c | 69 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-130.c | 69 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-131.c | 69 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-132.c | 59 +++++++++ .../riscv/rvv/base/binop_vx_constraint-133.c | 69 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-134.c | 69 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-135.c | 69 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-136.c | 59 +++++++++ .../riscv/rvv/base/binop_vx_constraint-137.c | 123 +++++++++++++++++++ .../riscv/rvv/base/binop_vx_constraint-138.c | 123 +++++++++++++++++++ .../riscv/rvv/base/binop_vx_constraint-139.c | 72 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-140.c | 72 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-141.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-142.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-143.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-144.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-145.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-146.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-147.c | 19 +++ .../riscv/rvv/base/binop_vx_constraint-148.c | 20 ++++ .../riscv/rvv/base/binop_vx_constraint-149.c | 19 +++ .../riscv/rvv/base/binop_vx_constraint-150.c | 21 ++++ .../riscv/rvv/base/binop_vx_constraint-151.c | 20 ++++ .../riscv/rvv/base/binop_vx_constraint-152.c | 20 ++++ .../riscv/rvv/base/binop_vx_constraint-153.c | 75 ++++++++++++ .../riscv/rvv/base/binop_vx_constraint-154.c | 69 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-155.c | 69 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-156.c | 65 ++++++++++ .../riscv/rvv/base/binop_vx_constraint-157.c | 133 +++++++++++++++++++++ .../riscv/rvv/base/binop_vx_constraint-158.c | 69 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-159.c | 65 ++++++++++ .../riscv/rvv/base/binop_vx_constraint-160.c | 133 +++++++++++++++++++++ .../riscv/rvv/base/binop_vx_constraint-161.c | 76 ++++++++++++ .../riscv/rvv/base/binop_vx_constraint-162.c | 17 +++ .../riscv/rvv/base/binop_vx_constraint-163.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-164.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-165.c | 13 ++ .../riscv/rvv/base/binop_vx_constraint-166.c | 15 +++ 50 files changed, 2276 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-2.c new file mode 100644 index 00000000000..6a03b00a3a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out) +{ + vint32mf2_t v = __riscv_vle32_v_i32mf2 (in, 4); + vbool64_t mask = __riscv_vlm_v_b64 (in + 1, 4); + vint32mf2_t v2 = __riscv_vle32_v_i32mf2 (in+444, 4); + vbool64_t mask2 = __riscv_vmseq_vv_i32mf2_b64_m(mask,v,v2,4); + mask2 = __riscv_vmslt_vv_i32mf2_b64_mu(mask2,mask2,v2,v,4); + __riscv_vsm_v_b64 (out, mask2, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-3.c new file mode 100644 index 00000000000..c4f81382a5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-3.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_m (m3, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_m (m3, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-4.c new file mode 100644 index 00000000000..e16db932f15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-4.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_mu (m3, m3, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_mu (m3, m3, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-5.c new file mode 100644 index 00000000000..54a240f44fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-5.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_mu (mask, m3, v, v, 4); + m4 = __riscv_vmseq_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_mu (mask, m3, v, v, 4); + m4 = __riscv_vmslt_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {vmv} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-6.c new file mode 100644 index 00000000000..ad5441f3404 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-6.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in, 4); + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v2, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_mu (m3, mask, v, v, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in, 4); + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v2, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_mu (m3, mask, v, v, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {vmv} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-7.c new file mode 100644 index 00000000000..0ef92a22a34 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-7.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_m (m3, v2, v2, 4); + m4 = __riscv_vmseq_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_m (m3, v2, v2, 4); + m4 = __riscv_vmslt_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-123.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-123.c new file mode 100644 index 00000000000..f11219c5221 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-123.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x) +{ + vint32mf2_t v = __riscv_vle32_v_i32mf2 (in, 4); + vbool64_t mask = __riscv_vlm_v_b64 (in + 1, 4); + vint32mf2_t v2 = __riscv_vle32_v_i32mf2 (in+444, 4); + vbool64_t mask2 = __riscv_vmseq_vx_i32mf2_b64_m(mask,v,x,4); + mask2 = __riscv_vmslt_vx_i32mf2_b64_mu(mask2,mask2,v2,x,4); + __riscv_vsm_v_b64 (out, mask2, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-124.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-124.c new file mode 100644 index 00000000000..f6c3015872f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-124.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_m (m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_m (m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-125.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-125.c new file mode 100644 index 00000000000..d92e250dcf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-125.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (m3, m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (m3, m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-126.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-126.c new file mode 100644 index 00000000000..57971915ad8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-126.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (mask, m3, v, x, 4); + m4 = __riscv_vmseq_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (mask, m3, v, x, 4); + m4 = __riscv_vmslt_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {vmv} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-127.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-127.c new file mode 100644 index 00000000000..3933c35f4ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-127.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in, 4); + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v2, x, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (m3, mask, v, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in, 4); + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v2, x, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (m3, mask, v, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {vmv} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-128.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-128.c new file mode 100644 index 00000000000..77c3a2b79e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-128.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_m (m3, v2, x, 4); + m4 = __riscv_vmseq_vx_i32m1_b32_m (m4, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_m (m3, v2, x, 4); + m4 = __riscv_vmslt_vx_i32m1_b32_m (m4, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c new file mode 100644 index 00000000000..db5dfe1fc3e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (m3, m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (mask, m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_m (m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c new file mode 100644 index 00000000000..da6b02ddd2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16,v0.t +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, -16, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (m3, m3, v2, -16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vmseq\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, -16, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (mask, m3, v2, -16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, -16, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_m (m3, v2, -16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c new file mode 100644 index 00000000000..16d35c8053d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15,v0.t +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, 15, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (m3, m3, v2, 15, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vmseq\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, 15, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (mask, m3, v2, 15, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, 15, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_m (m3, v2, 15, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-132.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-132.c new file mode 100644 index 00000000000..b804c15baa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-132.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (m3, m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** ... +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_mu (mask, m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** ... +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmseq_vx_i32m1_b32_m (m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c new file mode 100644 index 00000000000..2da8ab7c15e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (m3, m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (mask, m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_m (m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c new file mode 100644 index 00000000000..a83fee48494 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15,v0.t +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, -15, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (m3, m3, v2, -15, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmslt\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-15,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, -15, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (mask, m3, v2, -15, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, -15, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_m (m3, v2, -15, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c new file mode 100644 index 00000000000..767987657b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,v0.t +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (m3, m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmslt\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*16,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (mask, m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_m (m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-136.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-136.c new file mode 100644 index 00000000000..d938c20aadc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-136.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, 17, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (m3, m3, v2, 17, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** ... +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, 17, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_mu (mask, m3, v2, 17, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** ... +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vx_i32m1_b32 (v, 17, 4); + vbool32_t m4 = __riscv_vmslt_vx_i32m1_b32_m (m3, v2, 17, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-137.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-137.c new file mode 100644 index 00000000000..1825a6ab982 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-137.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16,v0.t +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, -16, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, -16, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15,v0.t +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 15, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 15, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 16, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 16, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 0xAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, x, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, x, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-138.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-138.c new file mode 100644 index 00000000000..1b19982f5d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-138.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15,v0.t +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, -15, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, -15, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,v0.t +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 16, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 16, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 17, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 17, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 0xAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, x, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, x, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-139.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-139.c new file mode 100644 index 00000000000..e062234b011 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-139.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16,v0.t +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, -16, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, -16, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15,v0.t +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 15, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 15, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 16, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 16, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 0xAAAAAAA, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 0xAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-140.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-140.c new file mode 100644 index 00000000000..a1dbf777c98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-140.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15,v0.t +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, -15, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, -15, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,v0.t +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 16, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 16, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 17, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 17, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 0xAAAAAAA, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 0xAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-141.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-141.c new file mode 100644 index 00000000000..7ff6affd3a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-141.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 0xAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-142.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-142.c new file mode 100644 index 00000000000..4613447f0d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-142.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 0xAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-143.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-143.c new file mode 100644 index 00000000000..7f44087a022 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-143.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-144.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-144.c new file mode 100644 index 00000000000..9ccbc15f666 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-144.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-145.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-145.c new file mode 100644 index 00000000000..3d73b2af4fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-145.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmseq_vx_i64m1_b64 (v2, x, 4); + vbool64_t v4 = __riscv_vmseq_vx_i64m1_b64_m (v3, v2, x, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-146.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-146.c new file mode 100644 index 00000000000..9aae1dc28f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-146.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmslt_vx_i64m1_b64 (v2, x, 4); + vbool64_t v4 = __riscv_vmslt_vx_i64m1_b64_m (v3, v2, x, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-147.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-147.c new file mode 100644 index 00000000000..bf08954797d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-147.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x) +{ + vint32mf2_t v = __riscv_vle32_v_i32mf2 (in, 4); + vbool64_t mask = __riscv_vlm_v_b64 (in + 1, 4); + vint32mf2_t v2 = __riscv_vle32_v_i32mf2 (in+444, 4); + vbool64_t mask2 = __riscv_vmsge_vx_i32mf2_b64_m(mask,v,x,4); + mask2 = __riscv_vmsge_vx_i32mf2_b64_mu(mask2,mask2,v2,x,4); + __riscv_vsm_v_b64 (out, mask2, 4); +} + +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-148.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-148.c new file mode 100644 index 00000000000..c48134bc553 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-148.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_m (m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmnot\.mm\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-149.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-149.c new file mode 100644 index 00000000000..7ba1a14aab6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-149.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (m3, m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmnot\.mm\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c new file mode 100644 index 00000000000..6282fb48105 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v, x, 4); + m4 = __riscv_vmsge_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmnot\.mm\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-151.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-151.c new file mode 100644 index 00000000000..a2aa633aef7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-151.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in, 4); + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v2, x, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (m3, mask, v, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmnot\.mm\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-152.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-152.c new file mode 100644 index 00000000000..1bd751564ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-152.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + //asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_m (m3, v2, x, 4); + m4 = __riscv_vmsge_vx_i32m1_b32_m (m4, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vmnot\.mm\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c new file mode 100644 index 00000000000..5a3d475e3d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c @@ -0,0 +1,75 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (m3, m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_m (m3, v2, x, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c new file mode 100644 index 00000000000..ddbde574565 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15,v0.t +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, -15, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (m3, m3, v2, -15, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmsge\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-15,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, -15, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v2, -15, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, -15, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_m (m3, v2, -15, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c new file mode 100644 index 00000000000..d22f3e4baa6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,v0.t +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (m3, m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmsge\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*16,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_m (m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-156.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-156.c new file mode 100644 index 00000000000..e2e75709709 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-156.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 17, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (m3, m3, v2, 17, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 17, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v2, 17, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 17, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_m (m3, v2, 17, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-157.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-157.c new file mode 100644 index 00000000000..2a9cb6eb6b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-157.c @@ -0,0 +1,133 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15,v0.t +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, -15, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, -15, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,v0.t +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 16, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 16, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 17, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 17, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 0xAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, x, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, x, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c new file mode 100644 index 00000000000..d22f3e4baa6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,v0.t +** vsm\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (m3, m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],mu +** vle32.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmsge\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*16,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,t[au],m[au] +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,\s*v0.t +** vsm.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 16, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_m (m3, v2, 16, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-159.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-159.c new file mode 100644 index 00000000000..e2e75709709 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-159.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f1 (void * in, void * in2, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1 (in2, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 17, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (m3, m3, v2, 17, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f2: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 17, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v2, 17, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* +** f3: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, 17, 4); + vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_m (m3, v2, 17, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-160.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-160.c new file mode 100644 index 00000000000..2a9cb6eb6b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-160.c @@ -0,0 +1,133 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15,v0.t +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, -15, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, -15, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,v0.t +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 16, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 16, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 17, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 17, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 0xAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, x, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, x, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-161.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-161.c new file mode 100644 index 00000000000..d95c7c6b6d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-161.c @@ -0,0 +1,76 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15,v0.t +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, -15, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, -15, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16 +** vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16,v0.t +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 16, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 16, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 17, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 17, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vmnot\.mm\s+v[0-9]+,\s*v[0-9]+ +** vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,v0.t +** vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 0xAAAAAAA, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 0xAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-162.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-162.c new file mode 100644 index 00000000000..976487a680c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-162.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 0xAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-163.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-163.c new file mode 100644 index 00000000000..9245f19c1db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-163.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-164.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-164.c new file mode 100644 index 00000000000..bd6916e9c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-164.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsge_vx_i64m1_b64 (v2, x, 4); + vbool64_t v4 = __riscv_vmsge_vx_i64m1_b64_m (v3, v2, x, 4); + __riscv_vsm_v_b64 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-165.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-165.c new file mode 100644 index 00000000000..313595e29cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-165.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vbool64_t v3 = __riscv_vmsgeu_vx_u64m1_b64 (v2, 0, 4); + __riscv_vsm_v_b64 (out + 2, v3, 4); +} + +/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-166.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-166.c new file mode 100644 index 00000000000..1bd52f4c1e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-166.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vbool64_t mask = __riscv_vlm_v_b64 (in,8); + vbool64_t mask2 = __riscv_vlm_v_b64 (in + 100,8); + vbool64_t v3 = __riscv_vmsgeu_vx_u64m1_b64_mu (mask,mask2,v2, 0, 4); + __riscv_vsm_v_b64 (out + 2, v3, 4); +} + +/* { dg-final { scan-assembler-times {vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */