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From: Kito Cheng <kito@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-6052] RISC-V: Add vnmsac vx rv64 C++ api tests Date: Wed, 15 Feb 2023 13:45:46 +0000 (GMT) [thread overview] Message-ID: <20230215134546.CB99938493D3@sourceware.org> (raw) https://gcc.gnu.org/g:7ce337324a8bafef59d268b647d3a03542c511bb commit r13-6052-g7ce337324a8bafef59d268b647d3a03542c511bb Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Date: Tue Feb 14 22:21:37 2023 +0800 RISC-V: Add vnmsac vx rv64 C++ api tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-3.C: New test. Diff: --- .../riscv/rvv/base/vnmsac_vx_mu_rv64-1.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-2.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-3.C | 292 +++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-1.C | 578 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-2.C | 578 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-3.C | 578 +++++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-1.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-2.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-3.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-1.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-2.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-3.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-1.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-2.C | 292 +++++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-3.C | 292 +++++++++++ 15 files changed, 5238 insertions(+) diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-1.C new file mode 100644 index 00000000000..d7b5f3b96b1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-2.C new file mode 100644 index 00000000000..d930cd0f10a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-3.C new file mode 100644 index 00000000000..56573a42a36 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-1.C new file mode 100644 index 00000000000..6ff4718a867 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,vl); +} + + +vint8mf8_t test___riscv_vnmsac(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-2.C new file mode 100644 index 00000000000..f3dd8c0fb7a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,31); +} + + +vint8mf8_t test___riscv_vnmsac(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-3.C new file mode 100644 index 00000000000..e8ef1727a35 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(vd,rs1,vs2,32); +} + + +vint8mf8_t test___riscv_vnmsac(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-1.C new file mode 100644 index 00000000000..ec6801a4f9c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-2.C new file mode 100644 index 00000000000..e46b2f94cd9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-3.C new file mode 100644 index 00000000000..17a0dd39d2d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tu(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-1.C new file mode 100644 index 00000000000..e404589f8c3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-2.C new file mode 100644 index 00000000000..4a1fcc9b1e7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-3.C new file mode 100644 index 00000000000..94fccae549f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-1.C new file mode 100644 index 00000000000..7c83dde7d75 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-2.C new file mode 100644 index 00000000000..0476655e254 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-3.C new file mode 100644 index 00000000000..44f70c69ed9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
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