From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <kito@sourceware.org>
Received: by sourceware.org (Postfix, from userid 2093)
	id 19995385B536; Wed, 15 Feb 2023 13:45:57 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 19995385B536
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1676468757;
	bh=8xwWtE8nvf8l6On/TMhY8seQkFTK/monefMEd/Kxia8=;
	h=From:To:Subject:Date:From;
	b=E+yj3h0mUkVPl6dfwE7eOWd+4swG2z1q2M1DaXUoH4zzBSKw1ds8M00JCVFYG3NWR
	 UjAhMCHnTCkfoJXB3wc8Ev4Jqc4WjCQLTVb0h0pO7L89o/u0leIYdAPOOz+KgJ1qVI
	 Q7sJPY7cn8fEaFxJPBl4RDJbEoMfg5kvdloLcKlc=
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Content-Type: text/plain; charset="utf-8"
From: Kito Cheng <kito@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r13-6054] RISC-V: Add vnmsac vv c++ api tests
X-Act-Checkin: gcc
X-Git-Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
X-Git-Refname: refs/heads/master
X-Git-Oldrev: 0fd29de569b0644b13e437b2b4eb072c076a159f
X-Git-Newrev: 47919b0decb469054a784ef32c98486074808d9d
Message-Id: <20230215134557.19995385B536@sourceware.org>
Date: Wed, 15 Feb 2023 13:45:57 +0000 (GMT)
List-Id: <gcc-cvs.sourceware.org>

https://gcc.gnu.org/g:47919b0decb469054a784ef32c98486074808d9d

commit r13-6054-g47919b0decb469054a784ef32c98486074808d9d
Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date:   Tue Feb 14 22:23:55 2023 +0800

    RISC-V: Add vnmsac vv c++ api tests
    
    gcc/testsuite/ChangeLog:
    
            * g++.target/riscv/rvv/base/vnmsac_vv-1.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv-2.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv-3.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_mu-1.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_mu-2.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_mu-3.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_tu-1.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_tu-2.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_tu-3.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_tum-1.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_tum-2.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_tum-3.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_tumu-1.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_tumu-2.C: New test.
            * g++.target/riscv/rvv/base/vnmsac_vv_tumu-3.C: New test.

Diff:
---
 .../g++.target/riscv/rvv/base/vnmsac_vv-1.C        | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv-2.C        | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv-3.C        | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_mu-1.C     | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_mu-2.C     | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_mu-3.C     | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_tu-1.C     | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_tu-2.C     | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_tu-3.C     | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_tum-1.C    | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_tum-2.C    | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_tum-3.C    | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-1.C   | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-2.C   | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-3.C   | 292 +++++++++++
 15 files changed, 5238 insertions(+)

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-1.C
new file mode 100644
index 00000000000..c8be480f24a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-1.C
@@ -0,0 +1,578 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,vl);
+}
+
+
+vint8mf8_t test___riscv_vnmsac(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-2.C
new file mode 100644
index 00000000000..5216084de11
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-2.C
@@ -0,0 +1,578 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,31);
+}
+
+
+vint8mf8_t test___riscv_vnmsac(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-3.C
new file mode 100644
index 00000000000..bf7d533c2e2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-3.C
@@ -0,0 +1,578 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,vs1,vs2,32);
+}
+
+
+vint8mf8_t test___riscv_vnmsac(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-1.C
new file mode 100644
index 00000000000..8e2e7d4abc5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-2.C
new file mode 100644
index 00000000000..08617a95146
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-3.C
new file mode 100644
index 00000000000..5582880625f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-1.C
new file mode 100644
index 00000000000..86420696d99
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tu(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tu(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tu(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tu(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tu(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tu(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tu(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tu(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tu(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tu(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tu(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tu(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tu(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tu(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tu(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tu(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tu(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tu(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tu(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tu(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tu(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tu(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tu(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tu(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tu(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tu(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tu(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tu(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tu(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tu(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tu(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tu(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tu(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tu(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tu(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tu(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tu(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tu(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tu(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tu(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tu(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tu(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tu(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tu(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-2.C
new file mode 100644
index 00000000000..eeb2dc89c8c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tu(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tu(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tu(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tu(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tu(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tu(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tu(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tu(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tu(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tu(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tu(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tu(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tu(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tu(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tu(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tu(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tu(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tu(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tu(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tu(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tu(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tu(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tu(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tu(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tu(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tu(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tu(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tu(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tu(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tu(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tu(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tu(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tu(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tu(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tu(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tu(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tu(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tu(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tu(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tu(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tu(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tu(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tu(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tu(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-3.C
new file mode 100644
index 00000000000..67e5c935e0e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tu(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tu(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tu(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tu(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tu(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tu(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tu(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tu(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tu(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tu(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tu(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tu(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tu(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tu(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tu(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tu(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tu(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tu(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tu(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tu(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tu(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tu(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tu(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tu(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tu(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tu(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tu(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tu(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tu(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tu(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tu(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tu(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tu(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tu(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tu(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tu(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tu(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tu(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tu(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tu(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tu(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tu(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tu(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tu(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-1.C
new file mode 100644
index 00000000000..0673cebfaee
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-2.C
new file mode 100644
index 00000000000..5645e74afe7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-3.C
new file mode 100644
index 00000000000..10d980af4f4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-1.C
new file mode 100644
index 00000000000..84af3ef7648
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-2.C
new file mode 100644
index 00000000000..4ee7e709142
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-3.C
new file mode 100644
index 00000000000..eea93f8cca9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */