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From: Alexandre Oliva <aoliva@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/aoliva/heads/testme)] [arm] disable aes-1742098 mitigation for a72 combine tests
Date: Thu, 16 Feb 2023 11:13:01 +0000 (GMT)	[thread overview]
Message-ID: <20230216111301.074EF3858031@sourceware.org> (raw)

https://gcc.gnu.org/g:87ed389a650fb6c0e696e378cb62e954224d9c7b

commit 87ed389a650fb6c0e696e378cb62e954224d9c7b
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Thu Feb 16 06:52:25 2023 -0300

    [arm] disable aes-1742098 mitigation for a72 combine tests
    
    The expected asm output for aes-fuse-[12].c does not correspond to
    that which is generated when -mfix-cortex-a57-aes-1742098 is enabled.
    It was introduced after the test, and enabled by default for the
    selected processor.  Disabling the option restores the circumstance
    that was tested for.
    
    
    for  gcc/testsuite/ChangeLog
    
            * gcc.target/arm/aes-fuse-1.c: Add
            -mno-fix-cortex-a57-aes-1742098.
            * gcc.target/arm/aes-fuse-2.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/arm/aes-fuse-1.c | 4 ++++
 gcc/testsuite/gcc.target/arm/aes-fuse-2.c | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/gcc/testsuite/gcc.target/arm/aes-fuse-1.c b/gcc/testsuite/gcc.target/arm/aes-fuse-1.c
index 27b08aeef7b..6ffb4991cca 100644
--- a/gcc/testsuite/gcc.target/arm/aes-fuse-1.c
+++ b/gcc/testsuite/gcc.target/arm/aes-fuse-1.c
@@ -2,6 +2,10 @@
 /* { dg-require-effective-target arm_crypto_ok } */
 /* { dg-add-options arm_crypto } */
 /* { dg-additional-options "-mcpu=cortex-a72 -O3 -dp" } */
+/* The mitigation applies to a72 by default, and protects the CRYPTO_AES
+   inputs, such as the explicit xor ops, from being combined like test used to
+   expect.  */
+/* { dg-additional-options "-mno-fix-cortex-a57-aes-1742098" } */
 
 #include <arm_neon.h>
 
diff --git a/gcc/testsuite/gcc.target/arm/aes-fuse-2.c b/gcc/testsuite/gcc.target/arm/aes-fuse-2.c
index 1266a287531..b72479c0e57 100644
--- a/gcc/testsuite/gcc.target/arm/aes-fuse-2.c
+++ b/gcc/testsuite/gcc.target/arm/aes-fuse-2.c
@@ -2,6 +2,10 @@
 /* { dg-require-effective-target arm_crypto_ok } */
 /* { dg-add-options arm_crypto } */
 /* { dg-additional-options "-mcpu=cortex-a72 -O3 -dp" } */
+/* The mitigation applies to a72 by default, and protects the CRYPTO_AES
+   inputs, such as the explicit xor ops, from being combined like test used to
+   expect.  */
+/* { dg-additional-options "-mno-fix-cortex-a57-aes-1742098" } */
 
 #include <arm_neon.h>

                 reply	other threads:[~2023-02-16 11:13 UTC|newest]

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