From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 37D44385B508; Fri, 17 Feb 2023 02:47:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 37D44385B508 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676602024; bh=Xmiu1YzULNHo9ED5YLZ3w8m+7BWtKWo9/WrEmbEkX+Y=; h=From:To:Subject:Date:From; b=ZzAXmibq4fQ1PFE1CuVZ4CiBdsh2CFeHFqvhpGnk7+RvAUfQp2uFEoabn/86mpzOx zlsEMavSdEBaKWa0mpx+Odf/ZmTvNJHs9gNBuxjVEVF4KEBorqQtgo0j1M0bcY02af nfhPrOty0TNWTwU38m9R+rbNlB0cOSi/t8YimHgM= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-6106] RISC-V: Move saturating add/subtract md pattern location [NFC] X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 3b6d44f459d28ab17d42967ce1c0490397e30e40 X-Git-Newrev: 5804c20b13f28cf6c2e464003c338104bb508906 Message-Id: <20230217024704.37D44385B508@sourceware.org> Date: Fri, 17 Feb 2023 02:47:04 +0000 (GMT) List-Id: https://gcc.gnu.org/g:5804c20b13f28cf6c2e464003c338104bb508906 commit r13-6106-g5804c20b13f28cf6c2e464003c338104bb508906 Author: Ju-Zhe Zhong Date: Wed Feb 15 07:18:20 2023 +0800 RISC-V: Move saturating add/subtract md pattern location [NFC] gcc/ChangeLog: * config/riscv/vector.md (@pred_): Rearrange. (@pred__scalar): Ditto. (*pred__scalar): Ditto. (*pred__extended_scalar): Ditto. Diff: --- gcc/config/riscv/vector.md | 490 ++++++++++++++++++++++----------------------- 1 file changed, 245 insertions(+), 245 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index cc550b7458b..6c02cf3d568 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1336,7 +1336,6 @@ ;; - 11.9 Vector Integer Min/Max Instructions ;; - 11.10 Vector Single-Width Integer Multiply Instructions ;; - 11.11 Vector Integer Divide Instructions -;; - 12.1 Vector Single-Width Saturating Add and Subtract ;; ------------------------------------------------------------------------------- (define_insn "@pred_" @@ -1728,248 +1727,6 @@ [(set_attr "type" "vialu") (set_attr "mode" "")]) -;; Saturating Add and Subtract -(define_insn "@pred_" - [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr") - (if_then_else:VI - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_sat_int_binop:VI - (match_operand:VI 3 "" " vr, vr, vr, vr") - (match_operand:VI 4 "" "")) - (match_operand:VI 2 "vector_merge_operand" "0vu,0vu,0vu,0vu")))] - "TARGET_VECTOR" - "@ - v.vv\t%0,%3,%4%p1 - v.vv\t%0,%3,%4%p1 - v\t%0,%p1 - v\t%0,%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode. -(define_insn "@pred__scalar" - [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr") - (if_then_else:VI_QHS - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_plus_binop:VI_QHS - (vec_duplicate:VI_QHS - (match_operand: 4 "register_operand" " r, r")) - (match_operand:VI_QHS 3 "register_operand" " vr, vr")) - (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_insn "@pred__scalar" - [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr") - (if_then_else:VI_QHS - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_minus_binop:VI_QHS - (match_operand:VI_QHS 3 "register_operand" " vr, vr") - (vec_duplicate:VI_QHS - (match_operand: 4 "register_operand" " r, r"))) - (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_expand "@pred__scalar" - [(set (match_operand:VI_D 0 "register_operand") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 5 "vector_length_operand") - (match_operand 6 "const_int_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_plus_binop:VI_D - (vec_duplicate:VI_D - (match_operand: 4 "reg_or_int_operand")) - (match_operand:VI_D 3 "register_operand")) - (match_operand:VI_D 2 "vector_merge_operand")))] - "TARGET_VECTOR" - { - if (riscv_vector::has_vi_variant_p (, operands[4])) - operands[4] = force_reg (mode, operands[4]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_ (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - operands[4] = force_reg (mode, operands[4]); - }) - -(define_insn "*pred__scalar" - [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_plus_binop:VI_D - (vec_duplicate:VI_D - (match_operand: 4 "register_operand" " r, r")) - (match_operand:VI_D 3 "register_operand" " vr, vr")) - (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_insn "*pred__extended_scalar" - [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_plus_binop:VI_D - (vec_duplicate:VI_D - (sign_extend: - (match_operand: 4 "register_operand" " r, r"))) - (match_operand:VI_D 3 "register_operand" " vr, vr")) - (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_expand "@pred__scalar" - [(set (match_operand:VI_D 0 "register_operand") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 5 "vector_length_operand") - (match_operand 6 "const_int_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_minus_binop:VI_D - (match_operand:VI_D 3 "register_operand") - (vec_duplicate:VI_D - (match_operand: 4 "reg_or_int_operand"))) - (match_operand:VI_D 2 "vector_merge_operand")))] - "TARGET_VECTOR" - { - if (riscv_vector::has_vi_variant_p (, operands[4])) - operands[4] = force_reg (mode, operands[4]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_ (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - operands[4] = force_reg (mode, operands[4]); - }) - -(define_insn "*pred__scalar" - [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_minus_binop:VI_D - (match_operand:VI_D 3 "register_operand" " vr, vr") - (vec_duplicate:VI_D - (match_operand: 4 "register_operand" " r, r"))) - (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_insn "*pred__extended_scalar" - [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_minus_binop:VI_D - (match_operand:VI_D 3 "register_operand" " vr, vr") - (vec_duplicate:VI_D - (sign_extend: - (match_operand: 4 "register_operand" " r, r")))) - (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - ;; Multiply High instructions. (define_insn "@pred_mulh" [(set (match_operand:VFULLI 0 "register_operand" "=vd, vr") @@ -3220,12 +2977,255 @@ ;; ---- Predicated fixed-point operations ;; ------------------------------------------------------------------------------- ;; Includes: +;; - 12.1 Vector Single-Width Saturating Add and Subtract ;; - 12.2 Vector Single-Width Aaveraging Add and Subtract ;; - 12.3 Vector Single-Width Fractional Multiply with Rounding and Saturation -;; - 12.5 Vector Single-Width Scaling Shift Instructions -;; - 12.6 Vector Narrowing Fixed-Point Clip Instructions +;; - 12.4 Vector Single-Width Scaling Shift Instructions +;; - 12.5 Vector Narrowing Fixed-Point Clip Instructions ;; ------------------------------------------------------------------------------- +;; Saturating Add and Subtract +(define_insn "@pred_" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_sat_int_binop:VI + (match_operand:VI 3 "" " vr, vr, vr, vr") + (match_operand:VI 4 "" "")) + (match_operand:VI 2 "vector_merge_operand" "0vu,0vu,0vu,0vu")))] + "TARGET_VECTOR" + "@ + v.vv\t%0,%3,%4%p1 + v.vv\t%0,%3,%4%p1 + v\t%0,%p1 + v\t%0,%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode. +(define_insn "@pred__scalar" + [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr") + (if_then_else:VI_QHS + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_plus_binop:VI_QHS + (vec_duplicate:VI_QHS + (match_operand: 4 "register_operand" " r, r")) + (match_operand:VI_QHS 3 "register_operand" " vr, vr")) + (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_insn "@pred__scalar" + [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr") + (if_then_else:VI_QHS + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_minus_binop:VI_QHS + (match_operand:VI_QHS 3 "register_operand" " vr, vr") + (vec_duplicate:VI_QHS + (match_operand: 4 "register_operand" " r, r"))) + (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_expand "@pred__scalar" + [(set (match_operand:VI_D 0 "register_operand") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 5 "vector_length_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_plus_binop:VI_D + (vec_duplicate:VI_D + (match_operand: 4 "reg_or_int_operand")) + (match_operand:VI_D 3 "register_operand")) + (match_operand:VI_D 2 "vector_merge_operand")))] + "TARGET_VECTOR" + { + if (riscv_vector::has_vi_variant_p (, operands[4])) + operands[4] = force_reg (mode, operands[4]); + else if (!TARGET_64BIT) + { + rtx v = gen_reg_rtx (mode); + + if (immediate_operand (operands[4], Pmode)) + operands[4] = gen_rtx_SIGN_EXTEND (mode, + force_reg (Pmode, operands[4])); + else + { + if (CONST_INT_P (operands[4])) + operands[4] = force_reg (mode, operands[4]); + + riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), + v, operands[4], operands[5], mode); + emit_insn (gen_pred_ (operands[0], operands[1], + operands[2], operands[3], v, operands[5], + operands[6], operands[7], operands[8])); + DONE; + } + } + else + operands[4] = force_reg (mode, operands[4]); + }) + +(define_insn "*pred__scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_plus_binop:VI_D + (vec_duplicate:VI_D + (match_operand: 4 "register_operand" " r, r")) + (match_operand:VI_D 3 "register_operand" " vr, vr")) + (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_insn "*pred__extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_plus_binop:VI_D + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 4 "register_operand" " r, r"))) + (match_operand:VI_D 3 "register_operand" " vr, vr")) + (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_expand "@pred__scalar" + [(set (match_operand:VI_D 0 "register_operand") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 5 "vector_length_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_minus_binop:VI_D + (match_operand:VI_D 3 "register_operand") + (vec_duplicate:VI_D + (match_operand: 4 "reg_or_int_operand"))) + (match_operand:VI_D 2 "vector_merge_operand")))] + "TARGET_VECTOR" + { + if (riscv_vector::has_vi_variant_p (, operands[4])) + operands[4] = force_reg (mode, operands[4]); + else if (!TARGET_64BIT) + { + rtx v = gen_reg_rtx (mode); + + if (immediate_operand (operands[4], Pmode)) + operands[4] = gen_rtx_SIGN_EXTEND (mode, + force_reg (Pmode, operands[4])); + else + { + if (CONST_INT_P (operands[4])) + operands[4] = force_reg (mode, operands[4]); + + riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), + v, operands[4], operands[5], mode); + emit_insn (gen_pred_ (operands[0], operands[1], + operands[2], operands[3], v, operands[5], + operands[6], operands[7], operands[8])); + DONE; + } + } + else + operands[4] = force_reg (mode, operands[4]); + }) + +(define_insn "*pred__scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_minus_binop:VI_D + (match_operand:VI_D 3 "register_operand" " vr, vr") + (vec_duplicate:VI_D + (match_operand: 4 "register_operand" " r, r"))) + (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_insn "*pred__extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_minus_binop:VI_D + (match_operand:VI_D 3 "register_operand" " vr, vr") + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 4 "register_operand" " r, r")))) + (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + (define_insn "@pred_" [(set (match_operand:VI 0 "register_operand" "=vd, vr") (if_then_else:VI