From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1363) id 322AF3858C1F; Mon, 20 Feb 2023 22:18:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 322AF3858C1F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676931516; bh=+jOHVJsdoav8uNNqWwTiIz6ZcZ0TzWDTLnaeiLWYvKw=; h=From:To:Subject:Date:From; b=iaVyidAKkdd47tnpfptbqQcDdR/1439lsChZiLvOtrLGRDq1n+aUlAf+FtMdL69pH D7a9DtwKZNcDNV8LsK0bc3qsNsWSJHDDt1ZeOCUyPE8UWaMdYErLBX22CbARJYvLSJ zAv2JD438DEUgwU4jXiuXh4d8Es9+vL4qIx1C4iQ= MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: Uros Bizjak To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-6148] i386: Introduce general_x64constmem_operand predicate X-Act-Checkin: gcc X-Git-Author: Uros Bizjak X-Git-Refname: refs/heads/master X-Git-Oldrev: cd8b4fae52d02541c2d8bd2200caad3812f37368 X-Git-Newrev: 1eb68d9f414313da853da94fe1581256405c3e05 Message-Id: <20230220221836.322AF3858C1F@sourceware.org> Date: Mon, 20 Feb 2023 22:18:36 +0000 (GMT) List-Id: https://gcc.gnu.org/g:1eb68d9f414313da853da94fe1581256405c3e05 commit r13-6148-g1eb68d9f414313da853da94fe1581256405c3e05 Author: Uros Bizjak Date: Mon Feb 20 23:17:20 2023 +0100 i386: Introduce general_x64constmem_operand predicate Instructions that use high-part QImode registers can not be encoded with REX prefix. To avoid REX prefix, operand constraints allow only legacy QImode registers, immediates and constant memory operands. The patch introduces matching predicate, so invalid operands are not combined into instruction RTX only to be later fixed up by reload pass. 2023-02-20 Uroš Bizjak gcc/ChangeLog: * config/i386/predicates.md (general_x64constmem_operand): New predicate. * config/i386/i386.md (*cmpqi_ext_1): Use nonimm_x64constmem_operand. (*cmpqi_ext_3): Use general_x64constmem_operand. (*addqi_ext_1): Ditto. (*testqi_ext_1): Ditto. (*andqi_ext_1): Ditto. (*andqi_ext_1_cc): Ditto. (*qi_ext_1): Ditto. (*xorqi_ext_1_cc): Ditto. Diff: --- gcc/config/i386/i386.md | 16 ++++++++-------- gcc/config/i386/predicates.md | 7 +++++++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 6382cfbce21..8ebb12be2c9 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1456,7 +1456,7 @@ (define_insn "*cmpqi_ext_1" [(set (reg FLAGS_REG) (compare - (match_operand:QI 0 "nonimmediate_operand" "QBc,m") + (match_operand:QI 0 "nonimm_x64constmem_operand" "QBc,m") (subreg:QI (zero_extract:SWI248 (match_operand 1 "int248_register_operand" "Q,Q") @@ -1501,7 +1501,7 @@ (match_operand 0 "int248_register_operand" "Q,Q") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "general_operand" "QnBc,m")))] + (match_operand:QI 1 "general_x64constmem_operand" "QnBc,m")))] "ix86_match_ccmode (insn, CCmode)" "cmp{b}\t{%1, %h0|%h0, %1}" [(set_attr "isa" "*,nox64") @@ -6683,7 +6683,7 @@ (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) 0)) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0)) (clobber (reg:CC FLAGS_REG))] "/* FIXME: without this LRA can't reload this pattern, see PR82524. */ rtx_equal_p (operands[0], operands[1])" @@ -9901,7 +9901,7 @@ (match_operand 0 "int248_register_operand" "Q,Q") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "general_operand" "QnBc,m")) + (match_operand:QI 1 "general_x64constmem_operand" "QnBc,m")) (const_int 0)))] "ix86_match_ccmode (insn, CCNOmode)" "test{b}\t{%1, %h0|%h0, %1}" @@ -10602,7 +10602,7 @@ (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) 0)) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0)) (clobber (reg:CC FLAGS_REG))] "/* FIXME: without this LRA can't reload this pattern, see PR82524. */ rtx_equal_p (operands[0], operands[1])" @@ -10622,7 +10622,7 @@ (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) (const_int 0))) (set (zero_extract:SWI248 (match_operand 0 "int248_register_operand" "+Q,Q") @@ -11345,7 +11345,7 @@ (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) 0)) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0)) (clobber (reg:CC FLAGS_REG))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) /* FIXME: without this LRA can't reload this pattern, see PR82524. */ @@ -11473,7 +11473,7 @@ (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) (const_int 0))) (set (zero_extract:SWI248 (match_operand 0 "int248_register_operand" "+Q,Q") diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 7b3db0cc851..b4d9ab40ab9 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -116,6 +116,13 @@ (ior (not (match_test "TARGET_64BIT")) (match_test "constant_address_p (XEXP (op, 0))"))))) +;; Match general operand, but exclude non-constant addresses for x86_64. +(define_predicate "general_x64constmem_operand" + (ior (match_operand 0 "nonmemory_operand") + (and (match_operand 0 "memory_operand") + (ior (not (match_test "TARGET_64BIT")) + (match_test "constant_address_p (XEXP (op, 0))"))))) + ;; Match register operands, but include memory operands for TARGET_SSE_MATH. (define_predicate "register_ssemem_operand" (if_then_else