From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D7BDD3858C00; Mon, 27 Feb 2023 22:58:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D7BDD3858C00 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1677538690; bh=LNveI2YWzCS5M92fFEpbJsROsdYbL+P1lpR3M+23vVo=; h=From:To:Subject:Date:From; b=WaZqoDPMbDpRLsF2NVJd7sL2T1eAla3Bh7w9Bs1F3sR3OErm4pK1vmS10g6n7xYOW bEZvrQJqI/YOWDx+WJ9+tJEBEp4oyta0QpnEmVwDIJRABdxZdrlJjs47WDHBrAXpN4 WNaJXw5OtDFSZAJ0gsamcPERFlk9cIe0GRl9iCDc= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf009)] Support load/store vector with right length. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf009 X-Git-Oldrev: b32beca550cbcc0be4878df3cf02f874d51df29b X-Git-Newrev: 4408d76f77d5c7225d2ab73f3dff69f76f63ccb2 Message-Id: <20230227225810.D7BDD3858C00@sourceware.org> Date: Mon, 27 Feb 2023 22:58:10 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4408d76f77d5c7225d2ab73f3dff69f76f63ccb2 commit 4408d76f77d5c7225d2ab73f3dff69f76f63ccb2 Author: Michael Meissner Date: Fri Feb 17 15:19:54 2023 -0500 Support load/store vector with right length. This patch adds support for new instructions that may be added to the PowerPC architecture in the future to enhance the load and store vector with length instructions. The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use since the count for the number of bytes must be in the top 8 bits of the GPR register, instead of the bottom 8 bits. This meant that code generating these instructions typically had to do a shift left by 56 bits to get the count into the right position. In a future version of the PowerPC architecture, new variants of these instructions might be added that expect the count to be in the bottom 8 bits of the GPR register. These patches add this support to GCC if the user uses the -mcpu=future option. I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl future lxvll/stxvll instructions would generate these instructions on 32-bit. However the patterns for these instructions is only done on 64-bit systems. So I added a check for 64-bit support before generating the instructions. I tested this patch on a little endian power10 system with long double using the tradiational IBM double double format. Assuming the other 6 patches for -mcpu=future are checked in (or at least the first patch), can I check this patch into the master branch for GCC 13? 2023-02-17 Michael Meissner gcc/ * config/rs6000/rs6000-string.cc (expand_block_move): Do generate lxvl and stxvl on 32-bit. * config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with the shift count automaticaly used in the insn. (lxvrl): New insn for -mcpu=future. (lxvrll): Likewise. (stxvl): If -mcpu=future, generate the stxvl with the shift count automaticaly used in the insn. (stxvrl): New insn for -mcpu=future. (stxvrll): Likewise. gcc/testsuite/ * gcc.target/powerpc/lxvrl.c: New test. * lib/target-supports.exp (check_effective_target_powerpc_future_ok): New effective target. Diff: --- gcc/testsuite/lib/target-supports.exp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 3e688ad7d79..8502215fed7 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6585,8 +6585,8 @@ proc check_effective_target_power10_ok { } { } } -# Return 1 if this is a PowerPC target supporting -mcpu=future or -mdense-math -# which enables the dense math operations. +# Return 1 if this is a PowerPC target supporting -mcpu=future which enables +# the dense math operations. proc check_effective_target_powerpc_dense_math_ok { } { return [check_no_compiler_messages_nocache powerpc_dense_math_ok assembly { __vector_quad vq;