From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7899) id 5D2E83858D3C; Wed, 1 Mar 2023 14:17:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5D2E83858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1677680272; bh=PnqnwJYnJLtF3xrTsKw+UI0eXLiBq4aKObSGm9Dxijo=; h=From:To:Subject:Date:From; b=sFpdH1qsOTVIo+0WDANE0/WGc/5Q5lVf6lGAn0yCPeGCvn9DBShPTUm834Y3GxLSs 4Tgkt7bpHsXbXVGwIlPA9B9MLicjex0ICqTSl/K4pwsu+nNMHP2IBGQhezJ0CikKUj DD7mSueRQ8fG7Sg00/jczZ/HXdFKEZaRMC/BG2Ko= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Paul-Antoine Arras To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/parras/heads/cond_fminmax_pattern)] cond_fminmax_pattern + minmaxop + tests X-Act-Checkin: gcc X-Git-Author: Paul-Antoine Arras X-Git-Refname: refs/users/parras/heads/cond_fminmax_pattern X-Git-Oldrev: b800f80b9c866df5ecaff744149ea695c0e24718 X-Git-Newrev: 92111e17a1111a599b1abb6eca8e5cfc8ff5a7f9 Message-Id: <20230301141752.5D2E83858D3C@sourceware.org> Date: Wed, 1 Mar 2023 14:17:51 +0000 (GMT) List-Id: https://gcc.gnu.org/g:92111e17a1111a599b1abb6eca8e5cfc8ff5a7f9 commit 92111e17a1111a599b1abb6eca8e5cfc8ff5a7f9 Author: Paul-Antoine Arras Date: Wed Feb 1 17:54:08 2023 +0100 cond_fminmax_pattern + minmaxop + tests Diff: --- gcc/config/gcn/gcn-valu.md | 133 +++++++++++++++++++++++ gcc/config/gcn/gcn.cc | 2 +- gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c | 34 ++++++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c | 32 ++++++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c | 35 ++++++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c | 31 ++++++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c | 34 ++++++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c | 32 ++++++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c | 34 ++++++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c | 32 ++++++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c | 8 ++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c | 4 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c | 8 ++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c | 4 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c | 8 ++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c | 4 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c | 8 ++ gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c | 4 + gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c | 9 ++ gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c | 5 + gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c | 9 ++ gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c | 5 + gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c | 9 ++ gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c | 5 + gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c | 9 ++ gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c | 5 + gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c | 9 ++ gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c | 4 + gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c | 9 ++ gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c | 4 + gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c | 9 ++ gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c | 4 + gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c | 9 ++ gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c | 4 + gcc/testsuite/gcc.target/gcn/cond_smax_1.c | 56 ++++++++++ gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c | 53 +++++++++ gcc/testsuite/gcc.target/gcn/cond_smin_1.c | 54 +++++++++ gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c | 53 +++++++++ gcc/testsuite/gcc.target/gcn/cond_umax_1.c | 51 +++++++++ gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c | 53 +++++++++ gcc/testsuite/gcc.target/gcn/cond_umin_1.c | 50 +++++++++ gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c | 53 +++++++++ gcc/testsuite/gcc.target/gcn/smax_1.c | 47 ++++++++ gcc/testsuite/gcc.target/gcn/smax_1_run.c | 49 +++++++++ gcc/testsuite/gcc.target/gcn/smin_1.c | 47 ++++++++ gcc/testsuite/gcc.target/gcn/smin_1_run.c | 49 +++++++++ gcc/testsuite/gcc.target/gcn/umax_1.c | 44 ++++++++ gcc/testsuite/gcc.target/gcn/umax_1_run.c | 49 +++++++++ gcc/testsuite/gcc.target/gcn/umin_1.c | 44 ++++++++ gcc/testsuite/gcc.target/gcn/umin_1_run.c | 49 +++++++++ 50 files changed, 1355 insertions(+), 1 deletion(-) diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 47d9d87d58a..acfe77ec33a 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2358,6 +2358,34 @@ DONE; }) +(define_expand "3_exec" + [(set (match_operand:V_QIHI 0 "gcn_valu_dst_operand") + (vec_merge:V_QIHI + (minmaxop:V_QIHI + (match_operand:V_QIHI 1 "gcn_valu_src0_operand") + (match_operand:V_QIHI 2 "gcn_valu_src1com_operand")) + (match_operand:V_QIHI 3 "gcn_register_or_unspec_operand" "U0") + (match_operand:DI 4 "gcn_exec_reg_operand" "e")))] + "" + { + enum {smin, umin, smax, umax}; + bool unsignedp = ( == umax || == umin); + rtx insi1 = gen_reg_rtx (mode); + rtx insi2 = gen_reg_rtx (mode); + rtx outsi = gen_reg_rtx (mode); + rtx out = operands[0]; + rtx exec = operands[4]; + rtx tmp = gen_reg_rtx (mode); + + convert_move (insi1, operands[1], unsignedp); + convert_move (insi2, operands[2], unsignedp); + emit_insn (gen_3_exec (outsi, insi1, insi2, + gcn_gen_undef(mode), exec)); + convert_move (tmp, outsi, unsignedp); + emit_insn (gen_mov_exec (out, tmp, operands[3], exec)); + DONE; + }) + (define_insn "3" [(set (match_operand:V_SI 0 "gcn_valu_dst_operand" "= v,RD") (minmaxop:V_SI @@ -2370,6 +2398,69 @@ [(set_attr "type" "vop2,ds") (set_attr "length" "8,8")]) +(define_insn_and_split "3" + [(set (match_operand:V_DI 0 "register_operand" "= v") + (minmaxop:V_DI + (match_operand:V_DI 1 "gcn_alu_operand" "% v") + (match_operand:V_DI 2 "gcn_alu_operand" " v"))) + (clobber (reg:DI VCC_REG))] + "" + "#" + "reload_completed" + [(const_int 0)] + { + rtx out = operands[0]; + rtx vcc = gen_rtx_REG (DImode, VCC_REG); + + enum {smin, smax, umin, umax}; + bool minp = ( == smin || == umin); + if ( == smin || == smax) + emit_insn (gen_vec_cmpdi (vcc, minp ? gen_rtx_LT (VOIDmode, 0, 0) : + gen_rtx_GT (VOIDmode, 0, 0), operands[1], operands[2])); + else + emit_insn (gen_vec_cmpdi (vcc, minp ? gen_rtx_LTU (VOIDmode, 0, 0) : + gen_rtx_GTU (VOIDmode, 0, 0), operands[1], operands[2])); + emit_insn (gen_vcond_mask_di (out, operands[1], operands[2], vcc)); + } + [(set_attr "type" "mult")]) + +(define_insn_and_split "3_exec" + [(set (match_operand:V_DI 0 "register_operand" "= v") + (vec_merge:V_DI + (minmaxop:V_DI + (match_operand:V_DI 1 "gcn_alu_operand" "% v") + (match_operand:V_DI 2 "gcn_alu_operand" " v")) + (match_operand:V_DI 3 "gcn_register_or_unspec_operand" " U0") + (match_operand:DI 4 "gcn_exec_reg_operand" "+e"))) + (clobber (match_scratch: 5 "= &v")) + (clobber (reg:DI VCC_REG))] + "" + "#" + "reload_completed" + [(const_int 0)] + { + rtx out = operands[0]; + rtx vcc = gen_rtx_REG (DImode, VCC_REG); + rtx exec = operands[4]; + rtx tmp = operands[5]; + + enum {smin, smax, umin, umax}; + bool minp = ( == smin || == umin); + if ( == smin || == smax) + emit_insn (gen_vec_cmpdi_exec (vcc, + minp ? gen_rtx_LT (VOIDmode, 0, 0) : + gen_rtx_GT (VOIDmode, 0, 0), operands[1], + operands[2], exec)); + else + emit_insn (gen_vec_cmpdi_exec (vcc, + minp ? gen_rtx_LTU (VOIDmode, 0, 0) : + gen_rtx_GTU (VOIDmode, 0, 0), operands[1], + operands[2], exec)); + emit_insn (gen_vcond_mask_di (tmp, operands[1], operands[2], vcc)); + emit_insn (gen_mov_exec (out, tmp, operands[3], exec)); + } + [(set_attr "type" "mult")]) + ;; }}} ;; {{{ Int unops @@ -3469,6 +3560,48 @@ }) ;; TODO smin umin smax umax +(define_code_iterator cond_fminmaxop [smin smax]) + +(define_expand "cond_" + [(match_operand:V_FP 0 "register_operand") + (match_operand:DI 1 "register_operand") + (cond_fminmaxop:V_FP + (match_operand:V_FP 2 "gcn_alu_operand") + (match_operand:V_FP 3 "gcn_alu_operand")) + (match_operand:V_FP 4 "register_operand")] + "" + { + operands[1] = force_reg (DImode, operands[1]); + operands[2] = force_reg (mode, operands[2]); + + emit_insn (gen_3_exec (operands[0], operands[2], + operands[3], operands[4], + operands[1])); + DONE; + }) + +(define_code_iterator cond_minmaxop [smin smax umin umax]) + +(define_expand "cond_" + [(match_operand:V_INT 0 "register_operand") + (match_operand:DI 1 "register_operand") + (cond_minmaxop:V_INT + (match_operand:V_INT 2 "gcn_alu_operand") + (match_operand:V_INT 3 "gcn_alu_operand")) + (match_operand:V_INT 4 "register_operand")] + "" + { + operands[1] = force_reg (DImode, operands[1]); + operands[2] = force_reg (mode, operands[2]); + rtx tmp = gen_reg_rtx (mode); + + emit_insn (gen_3_exec (tmp, operands[2], + operands[3], gcn_gen_undef(mode), + operands[1])); + emit_insn (gen_vcond_mask_di (operands[0], tmp, operands[4], operands[1])); + DONE; + }) + (define_code_iterator cond_bitop [and ior xor]) (define_expand "cond_" diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index 23ab01e75d8..b4216b73522 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -797,7 +797,7 @@ static reg_class_t gcn_spill_class (reg_class_t c, machine_mode /*mode */ ) { if (reg_classes_intersect_p (ALL_CONDITIONAL_REGS, c) - || c == VCC_CONDITIONAL_REG) + || c == VCC_CONDITIONAL_REG || c == EXEC_MASK_REG) return SGPR_REGS; else return NO_REGS; diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c new file mode 100644 index 00000000000..8ad968c339f --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#include + +#ifndef FN +#define FN(X) __builtin_fmax##X +#endif + +#define DEF_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? FN (y[i], CONST) : y[i]; \ + } + +#define TEST_TYPE(T, FN, TYPE, PRED_TYPE) \ + T (FN, TYPE, PRED_TYPE, zero, 0) \ + T (FN, TYPE, PRED_TYPE, one, 1) \ + T (FN, TYPE, PRED_TYPE, two, 2) + +#define TEST_ALL(T) \ + TEST_TYPE (T, FN (f32), float, int32_t) \ + TEST_TYPE (T, FN (f64), double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c new file mode 100644 index 00000000000..ed4b471ca4d --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#include "cond_fmaxnm_1.c" + +#define N 99 + +#define TEST_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? FN (y[i], CONST) : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c new file mode 100644 index 00000000000..a801778355a --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#include + +#ifndef FN +#define FN(X) __builtin_fmax##X +#endif + +#define DEF_LOOP(FN, TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + TYPE *__restrict z, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = y[i] < 8 ? FN (z[i], CONST) : y[i]; \ + } + +#define TEST_TYPE(T, FN, TYPE) \ + T (FN, TYPE, zero, 0) \ + T (FN, TYPE, one, 1) \ + T (FN, TYPE, two, 2) + +#define TEST_ALL(T) \ + TEST_TYPE (T, FN (f32), float) \ + TEST_TYPE (T, FN (f64), double) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ + diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c new file mode 100644 index 00000000000..970fd6cfe5a --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#include "cond_fmaxnm_2.c" + +#define N 99 + +#define TEST_LOOP(FN, TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N], z[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i % 13; \ + z[i] = i * i; \ + } \ + test_##TYPE##_##NAME (x, y, z, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = y[i] < 8 ? FN (z[i], CONST) : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c new file mode 100644 index 00000000000..002754819ad --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#include + +#ifndef FN +#define FN(X) __builtin_fmax##X +#endif + +#define DEF_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? FN (y[i], CONST) : 4; \ + } + +#define TEST_TYPE(T, FN, TYPE, PRED_TYPE) \ + T (FN, TYPE, PRED_TYPE, zero, 0) \ + T (FN, TYPE, PRED_TYPE, one, 1) \ + T (FN, TYPE, PRED_TYPE, two, 2) + +#define TEST_ALL(T) \ + TEST_TYPE (T, FN (f32), float, int32_t) \ + TEST_TYPE (T, FN (f64), double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c new file mode 100644 index 00000000000..469bee10678 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#include "cond_fmaxnm_3.c" + +#define N 99 + +#define TEST_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? FN (y[i], CONST) : 4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c new file mode 100644 index 00000000000..867b459e0db --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#include + +#ifndef FN +#define FN(X) __builtin_fmax##X +#endif + +#define DEF_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? FN (y[i], CONST) : 0; \ + } + +#define TEST_TYPE(T, FN, TYPE, PRED_TYPE) \ + T (FN, TYPE, PRED_TYPE, zero, 0) \ + T (FN, TYPE, PRED_TYPE, one, 1) \ + T (FN, TYPE, PRED_TYPE, two, 2) + +#define TEST_ALL(T) \ + TEST_TYPE (T, FN (f32), float, int32_t) \ + TEST_TYPE (T, FN (f64), double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c new file mode 100644 index 00000000000..874d1d3bb54 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#include "cond_fmaxnm_4.c" + +#define N 99 + +#define TEST_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? FN (y[i], CONST) : 0; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c new file mode 100644 index 00000000000..1fd7815e5f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fmaxnm_1.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c new file mode 100644 index 00000000000..8c0bc2ae876 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fmaxnm_1_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c new file mode 100644 index 00000000000..4ec60d3a90b --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fmaxnm_2.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c new file mode 100644 index 00000000000..5c5db46b390 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fmaxnm_2_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c new file mode 100644 index 00000000000..6c71a836140 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fmaxnm_3.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c new file mode 100644 index 00000000000..0abe626fdfb --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fmaxnm_3_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c new file mode 100644 index 00000000000..80e287b87b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fmaxnm_4.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c new file mode 100644 index 00000000000..43b892f922e --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fmaxnm_4_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c new file mode 100644 index 00000000000..cfb12c0a502 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_1.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c new file mode 100644 index 00000000000..6dd9d499b35 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_1_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c new file mode 100644 index 00000000000..5c6c333ab6d --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_2.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c new file mode 100644 index 00000000000..72784290113 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_2_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c new file mode 100644 index 00000000000..b13eabb73d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_3.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c new file mode 100644 index 00000000000..8c994cae202 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_3_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c new file mode 100644 index 00000000000..2a03bf97a2d --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_4.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c new file mode 100644 index 00000000000..728f4136015 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_4_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c new file mode 100644 index 00000000000..cf15929e26e --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_1.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c new file mode 100644 index 00000000000..9236ab5b211 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fminnm_1_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c new file mode 100644 index 00000000000..0a46fe281a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_2.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c new file mode 100644 index 00000000000..a5f90d9e76a --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fminnm_2_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c new file mode 100644 index 00000000000..679ae18e50e --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_3.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c new file mode 100644 index 00000000000..d7ad738db5c --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fminnm_3_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c new file mode 100644 index 00000000000..2d6a217429d --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmaxnm_4.c" + +/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c new file mode 100644 index 00000000000..3d92353ac55 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_fminnm_4_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c new file mode 100644 index 00000000000..3460d5c7b98 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -dp" } */ + +#include + +#define DO_REGREG_OPS(TYPE) \ + void __attribute__ ((noclone)) \ + varith_##TYPE##_reg (TYPE *__restrict x, TYPE *__restrict y, \ + TYPE *__restrict pred, int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = (pred[i] != -1) ? (x[i] > y[i] ? x[i] : y[i]) : -4; \ + } + +#define DO_IMMEDIATE_OPS(VALUE, TYPE, NAME) \ + void __attribute__ ((noclone)) \ + varithimm_##NAME##_##TYPE (TYPE *__restrict x, TYPE *__restrict pred, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = (pred[i] != -1) \ + ? (x[i] > (TYPE) VALUE ? x[i] : (TYPE) VALUE) \ + : -4; \ + } + +#define DO_ARITH_OPS(REG, IMM, TYPE) \ + REG (TYPE); \ + IMM (0, TYPE, 0); \ + IMM (86, TYPE, 86); \ + IMM (109, TYPE, 109); \ + IMM (141, TYPE, 141); \ + IMM (92137445376, TYPE, 92137445376); \ + IMM (-1, TYPE, minus1); \ + IMM (-110, TYPE, minus110); \ + IMM (-141, TYPE, minus141); \ + IMM (-92137445376, TYPE, minus92137445376); + + +#define TEST_ALL(REG, IMM) \ + DO_ARITH_OPS (REG, IMM, int8_t) \ + DO_ARITH_OPS (REG, IMM, int16_t) \ + DO_ARITH_OPS (REG, IMM, int32_t) \ + DO_ARITH_OPS (REG, IMM, int64_t) + +TEST_ALL(DO_REGREG_OPS, DO_IMMEDIATE_OPS) + +/* { dg-final { scan-assembler-times {smaxv64si3_exec} 30 } } */ +/* { dg-final { scan-assembler-not {smaxv64si3/0} } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_??} 240 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_??, 0} } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_gt_i32\tvcc, s[0-9]+, v[0-9]+} 80 } } */ +/* { dg-final { scan-assembler-not {\tv_cmpx_gt_i32\tvcc, s[0-9]+, v[0-9]+} } } */ +/* { dg-final { scan-assembler-not {\ts_cmpk_lg_u32\tvcc_lo, 0} } } */ +/* { dg-final { scan-assembler-times {vec_cmpv64didi_exec} 11 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_ne_u64\ts\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -1} 10 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_gt_i64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 10 } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c new file mode 100644 index 00000000000..c951e614579 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_smax_1.c" + +#define N 99 + +#define TEST_REGREG_OPS(TYPE) \ + { \ + TYPE x[N], y[N]; \ + TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i % 13; \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + varith_##TYPE##_reg (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != -1 ? (x[i] > y[i] ? x[i] : y[i]) : -4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +#define TEST_IMMEDIATE_OPS(VALUE, TYPE, NAME) \ + { \ + TYPE x[N], y[N]; \ + TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i * i; \ + pred[i] = i % 3; \ + } \ + varithimm_##NAME##_##TYPE (x, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected \ + = i % 3 != -1 ? (x[i] > (TYPE) VALUE ? x[i] : (TYPE) VALUE) : -4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_REGREG_OPS, TEST_IMMEDIATE_OPS) + return 0; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c new file mode 100644 index 00000000000..b19b6da5960 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -dp" } */ + +#include + +#define DO_REGREG_OPS(TYPE) \ + void __attribute__ ((noclone)) \ + varith_##TYPE##_reg (TYPE *__restrict x, TYPE *__restrict y, \ + TYPE *__restrict pred, int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = (pred[i] != -1) ? (x[i] < y[i] ? x[i] : y[i]) : -4; \ + } + +#define DO_IMMEDIATE_OPS(VALUE, TYPE, NAME) \ + void __attribute__ ((noclone)) \ + varithimm_##NAME##_##TYPE (TYPE *__restrict x, TYPE *__restrict pred, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] \ + = (pred[i] != -1) ? (x[i] < (TYPE) VALUE ? x[i] : (TYPE) VALUE) : -4; \ + } + +#define DO_ARITH_OPS(REG, IMM, TYPE) \ + REG (TYPE); \ + IMM (0, TYPE, 0); \ + IMM (86, TYPE, 86); \ + IMM (109, TYPE, 109); \ + IMM (141, TYPE, 141); \ + IMM (92137445376, TYPE, 92137445376); \ + IMM (-1, TYPE, minus1); \ + IMM (-110, TYPE, minus110); \ + IMM (-141, TYPE, minus141); \ + IMM (-92137445376, TYPE, minus92137445376); + +#define TEST_ALL(REG, IMM) \ + DO_ARITH_OPS (REG, IMM, int8_t) \ + DO_ARITH_OPS (REG, IMM, int16_t) \ + DO_ARITH_OPS (REG, IMM, int32_t) \ + DO_ARITH_OPS (REG, IMM, int64_t) + +TEST_ALL (DO_REGREG_OPS, DO_IMMEDIATE_OPS) + +/* { dg-final { scan-assembler-times {sminv64si3_exec} 30 } } */ +/* { dg-final { scan-assembler-not {sminv64si3/0} } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_??} 240 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_??, 0} } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_gt_i32\tvcc, s[0-9]+, v[0-9]+} 80 } } */ +/* { dg-final { scan-assembler-not {\tv_cmpx_gt_i32\tvcc, s[0-9]+, v[0-9]+} } } */ +/* { dg-final { scan-assembler-not {\ts_cmpk_lg_u32\tvcc_lo, 0} } } */ +/* { dg-final { scan-assembler-times {vec_cmpv64didi_exec} 11 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_ne_u64\ts\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -1} 10 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_lt_i64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 10 } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c new file mode 100644 index 00000000000..4d654e75226 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_smin_1.c" + +#define N 99 + +#define TEST_REGREG_OPS(TYPE) \ + { \ + TYPE x[N], y[N]; \ + TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i % 13; \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + varith_##TYPE##_reg (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != -1 ? (x[i] < y[i] ? x[i] : y[i]) : -4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +#define TEST_IMMEDIATE_OPS(VALUE, TYPE, NAME) \ + { \ + TYPE x[N], y[N]; \ + TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i * i; \ + pred[i] = i % 3; \ + } \ + varithimm_##NAME##_##TYPE (x, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected \ + = i % 3 != -1 ? (x[i] < (TYPE) VALUE ? x[i] : (TYPE) VALUE) : -4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_REGREG_OPS, TEST_IMMEDIATE_OPS) + return 0; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c new file mode 100644 index 00000000000..a2d48a5bcef --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -dp" } */ + +#include + +#define DO_REGREG_OPS(TYPE) \ + void __attribute__ ((noclone)) \ + varith_##TYPE##_reg (TYPE *__restrict x, TYPE *__restrict y, \ + TYPE *__restrict pred, int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = (pred[i] != 1) ? (x[i] > y[i] ? x[i] : y[i]) : 4; \ + } + +#define DO_IMMEDIATE_OPS(VALUE, TYPE) \ + void __attribute__ ((noclone)) \ + varithimm_##VALUE##_##TYPE (TYPE *__restrict x, TYPE *__restrict pred, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = (pred[i] != 1) ? (x[i] > (TYPE) VALUE ? x[i] : (TYPE) VALUE) : 4; \ + } + +#define DO_ARITH_OPS(REG, IMM, TYPE) \ + REG (TYPE); \ + IMM (2, TYPE); \ + IMM (86, TYPE); \ + IMM (109, TYPE); \ + IMM (141, TYPE); \ + IMM (229, TYPE); \ + IMM (255, TYPE); \ + IMM (992137445376, TYPE); + +#define TEST_ALL(REG, IMM) \ + DO_ARITH_OPS (REG, IMM, uint8_t) \ + DO_ARITH_OPS (REG, IMM, uint16_t) \ + DO_ARITH_OPS (REG, IMM, uint32_t) \ + DO_ARITH_OPS (REG, IMM, uint64_t) + +TEST_ALL (DO_REGREG_OPS, DO_IMMEDIATE_OPS) + +/* { dg-final { scan-assembler-times {umaxv64si3_exec} 20 } } */ +/* { dg-final { scan-assembler-not {umaxv64si3/0} } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_??} 168 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_??, 0} } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_gt_i32\tvcc, s[0-9]+, v[0-9]+} 56 } } */ +/* { dg-final { scan-assembler-not {\ts_cmpk_lg_u32\tvcc_lo, 0} } } */ +/* { dg-final { scan-assembler-times {vec_cmpv64didi_exec} 9 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_ne_u64\ts\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], 1} 8 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_gt_u64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 8 } } */ + diff --git a/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c new file mode 100644 index 00000000000..0abcf46dd6f --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_umax_1.c" + +#define N 99 + +#define TEST_REGREG_OPS(TYPE) \ + { \ + TYPE x[N], y[N]; \ + TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i % 13; \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + varith_##TYPE##_reg (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? (x[i] > y[i] ? x[i] : y[i]) : 4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +#define TEST_IMMEDIATE_OPS(VALUE, TYPE) \ + { \ + TYPE x[N], y[N]; \ + TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i * i; \ + pred[i] = i % 3; \ + } \ + varithimm_##VALUE##_##TYPE (x, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected \ + = i % 3 != 1 ? (x[i] > (TYPE) VALUE ? x[i] : (TYPE) VALUE) : 4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_REGREG_OPS, TEST_IMMEDIATE_OPS) + return 0; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c new file mode 100644 index 00000000000..f0b7a2d78dd --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -dp" } */ + +#include + +#define DO_REGREG_OPS(TYPE) \ + void __attribute__ ((noclone)) \ + varith_##TYPE##_reg (TYPE *__restrict x, TYPE *__restrict y, \ + TYPE *__restrict pred, int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = (pred[i] != 1) ? (x[i] < y[i] ? x[i] : y[i]) : 4; \ + } + +#define DO_IMMEDIATE_OPS(VALUE, TYPE) \ + void __attribute__ ((noclone)) \ + varithimm_##VALUE##_##TYPE (TYPE *__restrict x, TYPE *__restrict pred, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = (pred[i] != 1) ? (x[i] < (TYPE) VALUE ? x[i] : (TYPE) VALUE) : 4; \ + } + +#define DO_ARITH_OPS(REG, IMM, TYPE) \ + REG (TYPE); \ + IMM (2, TYPE); \ + IMM (86, TYPE); \ + IMM (109, TYPE); \ + IMM (141, TYPE); \ + IMM (229, TYPE); \ + IMM (255, TYPE); \ + IMM (992137445376, TYPE); + +#define TEST_ALL(REG, IMM) \ + DO_ARITH_OPS (REG, IMM, uint8_t) \ + DO_ARITH_OPS (REG, IMM, uint16_t) \ + DO_ARITH_OPS (REG, IMM, uint32_t) \ + DO_ARITH_OPS (REG, IMM, uint64_t) + +TEST_ALL (DO_REGREG_OPS, DO_IMMEDIATE_OPS) + +/* { dg-final { scan-assembler-times {uminv64si3_exec} 20 } } */ +/* { dg-final { scan-assembler-not {uminv64si3/0} } } */ +/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_??} 168 } } */ +/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_??, 0} } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_gt_i32\tvcc, s[0-9]+, v[0-9]+} 56 } } */ +/* { dg-final { scan-assembler-not {\ts_cmpk_lg_u32\tvcc_lo, 0} } } */ +/* { dg-final { scan-assembler-times {vec_cmpv64didi_exec} 9 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_ne_u64\ts\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], 1} 8 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_lt_u64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 8 } } */ diff --git a/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c new file mode 100644 index 00000000000..eda49ebc681 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_umin_1.c" + +#define N 99 + +#define TEST_REGREG_OPS(TYPE) \ + { \ + TYPE x[N], y[N]; \ + TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i % 13; \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + varith_##TYPE##_reg (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? (x[i] < y[i] ? x[i] : y[i]) : 4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +#define TEST_IMMEDIATE_OPS(VALUE, TYPE) \ + { \ + TYPE x[N], y[N]; \ + TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i * i; \ + pred[i] = i % 3; \ + } \ + varithimm_##VALUE##_##TYPE (x, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected \ + = i % 3 != 1 ? (x[i] < (TYPE) VALUE ? x[i] : (TYPE) VALUE) : 4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_REGREG_OPS, TEST_IMMEDIATE_OPS) + return 0; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/smax_1.c b/gcc/testsuite/gcc.target/gcn/smax_1.c new file mode 100644 index 00000000000..b9c24bea648 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/smax_1.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -dp" } */ + +#include + +#define DO_REGREG_OPS(TYPE) \ + void __attribute__ ((noclone)) \ + varith_##TYPE##_reg (TYPE *__restrict x, TYPE *__restrict y, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = x[i] > y[i] ? x[i] : y[i]; \ + } + +#define DO_IMMEDIATE_OPS(VALUE, TYPE, NAME) \ + void __attribute__ ((noclone)) \ + varithimm_##NAME##_##TYPE (TYPE *__restrict x, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = x[i] > (TYPE) VALUE ? x[i] : (TYPE) VALUE; \ + } + +#define DO_ARITH_OPS(REG, IMM, TYPE) \ + REG (TYPE); \ + IMM (0, TYPE, 0); \ + IMM (86, TYPE, 86); \ + IMM (109, TYPE, 109); \ + IMM (141, TYPE, 141); \ + IMM (92137445376, TYPE, 92137445376); \ + IMM (-1, TYPE, minus1); \ + IMM (-110, TYPE, minus110); \ + IMM (-141, TYPE, minus141); \ + IMM (-92137445376, TYPE, minus92137445376); + + +#define TEST_ALL(REG, IMM) \ + DO_ARITH_OPS (REG, IMM, int8_t) \ + DO_ARITH_OPS (REG, IMM, int16_t) \ + DO_ARITH_OPS (REG, IMM, int32_t) \ + DO_ARITH_OPS (REG, IMM, int64_t) + +TEST_ALL(DO_REGREG_OPS, DO_IMMEDIATE_OPS) + +/* { dg-final { scan-assembler-times {vec_cmpv64didi} 10 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_gt_i64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 10 } } */ +/* { dg-final { scan-assembler-times {\tv_cmpx_gt_i32\tvcc, s[0-9]+, v[0-9]+} 80 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/smax_1_run.c b/gcc/testsuite/gcc.target/gcn/smax_1_run.c new file mode 100644 index 00000000000..f12fef1d697 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/smax_1_run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "smax_1.c" + +#define N 99 + +#define TEST_REGREG_OPS(TYPE) \ + { \ + TYPE x[N], y[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i % 13; \ + y[i] = i * i; \ + } \ + varith_##TYPE##_reg (x, y, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = x[i] > y[i] ? x[i] : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +#define TEST_IMMEDIATE_OPS(VALUE, TYPE, NAME) \ + { \ + TYPE x[N], y[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i * i; \ + } \ + varithimm_##NAME##_##TYPE (x, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected \ + = x[i] > (TYPE) VALUE ? x[i] : (TYPE) VALUE; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_REGREG_OPS, TEST_IMMEDIATE_OPS) + return 0; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/smin_1.c b/gcc/testsuite/gcc.target/gcn/smin_1.c new file mode 100644 index 00000000000..9a2afccc471 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/smin_1.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -dp" } */ + +#include + +#define DO_REGREG_OPS(TYPE) \ + void __attribute__ ((noclone)) \ + varith_##TYPE##_reg (TYPE *__restrict x, TYPE *__restrict y, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = x[i] < y[i] ? x[i] : y[i]; \ + } + +#define DO_IMMEDIATE_OPS(VALUE, TYPE, NAME) \ + void __attribute__ ((noclone)) \ + varithimm_##NAME##_##TYPE (TYPE *__restrict x, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] \ + = x[i] < (TYPE) VALUE ? x[i] : (TYPE) VALUE; \ + } + +#define DO_ARITH_OPS(REG, IMM, TYPE) \ + REG (TYPE); \ + IMM (0, TYPE, 0); \ + IMM (86, TYPE, 86); \ + IMM (109, TYPE, 109); \ + IMM (141, TYPE, 141); \ + IMM (92137445376, TYPE, 92137445376); \ + IMM (-1, TYPE, minus1); \ + IMM (-110, TYPE, minus110); \ + IMM (-141, TYPE, minus141); \ + IMM (-92137445376, TYPE, minus92137445376); + +#define TEST_ALL(REG, IMM) \ + DO_ARITH_OPS (REG, IMM, int8_t) \ + DO_ARITH_OPS (REG, IMM, int16_t) \ + DO_ARITH_OPS (REG, IMM, int32_t) \ + DO_ARITH_OPS (REG, IMM, int64_t) + +TEST_ALL (DO_REGREG_OPS, DO_IMMEDIATE_OPS) + +/* { dg-final { scan-assembler-times {vec_cmpv64didi} 10 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_lt_i64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 10 } } */ +/* { dg-final { scan-assembler-times {\tv_cmpx_gt_i32\tvcc, s[0-9]+, v[0-9]+} 80 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/smin_1_run.c b/gcc/testsuite/gcc.target/gcn/smin_1_run.c new file mode 100644 index 00000000000..b57de12c17f --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/smin_1_run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "smin_1.c" + +#define N 99 + +#define TEST_REGREG_OPS(TYPE) \ + { \ + TYPE x[N], y[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i % 13; \ + y[i] = i * i; \ + } \ + varith_##TYPE##_reg (x, y, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = x[i] < y[i] ? x[i] : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +#define TEST_IMMEDIATE_OPS(VALUE, TYPE, NAME) \ + { \ + TYPE x[N], y[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i * i; \ + } \ + varithimm_##NAME##_##TYPE (x, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected \ + = x[i] < (TYPE) VALUE ? x[i] : (TYPE) VALUE; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_REGREG_OPS, TEST_IMMEDIATE_OPS) + return 0; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/umax_1.c b/gcc/testsuite/gcc.target/gcn/umax_1.c new file mode 100644 index 00000000000..31e18f012a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/umax_1.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -dp" } */ + +#include + +#define DO_REGREG_OPS(TYPE) \ + void __attribute__ ((noclone)) \ + varith_##TYPE##_reg (TYPE *__restrict x, TYPE *__restrict y, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = x[i] > y[i] ? x[i] : y[i]; \ + } + +#define DO_IMMEDIATE_OPS(VALUE, TYPE) \ + void __attribute__ ((noclone)) \ + varithimm_##VALUE##_##TYPE (TYPE *__restrict x, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = x[i] > (TYPE) VALUE ? x[i] : (TYPE) VALUE; \ + } + +#define DO_ARITH_OPS(REG, IMM, TYPE) \ + REG (TYPE); \ + IMM (2, TYPE); \ + IMM (86, TYPE); \ + IMM (109, TYPE); \ + IMM (141, TYPE); \ + IMM (229, TYPE); \ + IMM (255, TYPE); \ + IMM (992137445376, TYPE); + +#define TEST_ALL(REG, IMM) \ + DO_ARITH_OPS (REG, IMM, uint8_t) \ + DO_ARITH_OPS (REG, IMM, uint16_t) \ + DO_ARITH_OPS (REG, IMM, uint32_t) \ + DO_ARITH_OPS (REG, IMM, uint64_t) + +TEST_ALL (DO_REGREG_OPS, DO_IMMEDIATE_OPS) + +/* { dg-final { scan-assembler-times {vec_cmpv64didi} 8 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_gt_u64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 8 } } */ +/* { dg-final { scan-assembler-times {\tv_cmpx_gt_i32\tvcc, s[0-9]+, v[0-9]+} 56 } } */ diff --git a/gcc/testsuite/gcc.target/gcn/umax_1_run.c b/gcc/testsuite/gcc.target/gcn/umax_1_run.c new file mode 100644 index 00000000000..d047b7a0576 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/umax_1_run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "umax_1.c" + +#define N 99 + +#define TEST_REGREG_OPS(TYPE) \ + { \ + TYPE x[N], y[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i % 13; \ + y[i] = i * i; \ + } \ + varith_##TYPE##_reg (x, y, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = x[i] > y[i] ? x[i] : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +#define TEST_IMMEDIATE_OPS(VALUE, TYPE) \ + { \ + TYPE x[N], y[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i * i; \ + } \ + varithimm_##VALUE##_##TYPE (x, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected \ + = x[i] > (TYPE) VALUE ? x[i] : (TYPE) VALUE; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_REGREG_OPS, TEST_IMMEDIATE_OPS) + return 0; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/gcn/umin_1.c b/gcc/testsuite/gcc.target/gcn/umin_1.c new file mode 100644 index 00000000000..f7e39ea38f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/umin_1.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -dp" } */ + +#include + +#define DO_REGREG_OPS(TYPE) \ + void __attribute__ ((noclone)) \ + varith_##TYPE##_reg (TYPE *__restrict x, TYPE *__restrict y, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = x[i] < y[i] ? x[i] : y[i]; \ + } + +#define DO_IMMEDIATE_OPS(VALUE, TYPE) \ + void __attribute__ ((noclone)) \ + varithimm_##VALUE##_##TYPE (TYPE *__restrict x, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + x[i] = x[i] < (TYPE) VALUE ? x[i] : (TYPE) VALUE; \ + } + +#define DO_ARITH_OPS(REG, IMM, TYPE) \ + REG (TYPE); \ + IMM (2, TYPE); \ + IMM (86, TYPE); \ + IMM (109, TYPE); \ + IMM (141, TYPE); \ + IMM (229, TYPE); \ + IMM (255, TYPE); \ + IMM (992137445376, TYPE); + +#define TEST_ALL(REG, IMM) \ + DO_ARITH_OPS (REG, IMM, uint8_t) \ + DO_ARITH_OPS (REG, IMM, uint16_t) \ + DO_ARITH_OPS (REG, IMM, uint32_t) \ + DO_ARITH_OPS (REG, IMM, uint64_t) + +TEST_ALL (DO_REGREG_OPS, DO_IMMEDIATE_OPS) + +/* { dg-final { scan-assembler-times {vec_cmpv64didi} 8 } } */ +/* { dg-final { scan-assembler-times {\tv_cmp_lt_u64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 8 } } */ +/* { dg-final { scan-assembler-times {\tv_cmpx_gt_i32\tvcc, s[0-9]+, v[0-9]+} 56 } } */ diff --git a/gcc/testsuite/gcc.target/gcn/umin_1_run.c b/gcc/testsuite/gcc.target/gcn/umin_1_run.c new file mode 100644 index 00000000000..77a5df95b46 --- /dev/null +++ b/gcc/testsuite/gcc.target/gcn/umin_1_run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "umin_1.c" + +#define N 99 + +#define TEST_REGREG_OPS(TYPE) \ + { \ + TYPE x[N], y[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i % 13; \ + y[i] = i * i; \ + } \ + varith_##TYPE##_reg (x, y, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = x[i] < y[i] ? x[i] : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +#define TEST_IMMEDIATE_OPS(VALUE, TYPE) \ + { \ + TYPE x[N], y[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = i * i; \ + } \ + varithimm_##VALUE##_##TYPE (x, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected \ + = x[i] < (TYPE) VALUE ? x[i] : (TYPE) VALUE; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_REGREG_OPS, TEST_IMMEDIATE_OPS) + return 0; +} \ No newline at end of file