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From: Paul-Antoine Arras <parras@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/parras/heads/cond_fminmax_pattern)] Fix tests
Date: Wed, 1 Mar 2023 14:17:57 +0000 (GMT) [thread overview]
Message-ID: <20230301141757.6C93D3858426@sourceware.org> (raw)
https://gcc.gnu.org/g:5e7f6f0b3a858f07cbfe804eedccdcafb2cc39f5
commit 5e7f6f0b3a858f07cbfe804eedccdcafb2cc39f5
Author: Paul-Antoine Arras <pa@codesourcery.com>
Date: Wed Mar 1 15:13:54 2023 +0100
Fix tests
Diff:
---
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c | 10 ++++++----
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c | 8 ++++----
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c | 11 +++++++----
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c | 11 +++++++----
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c | 7 ++++---
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c | 7 ++++---
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c | 7 ++++---
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c | 7 ++++---
gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c | 7 ++++---
gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c | 9 +++++----
gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c | 11 +++++++----
gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c | 11 +++++++----
gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c | 7 ++++---
gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c | 7 ++++---
gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c | 9 +++++----
gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c | 9 +++++----
gcc/testsuite/gcc.target/gcn/cond_smax_1.c | 2 --
gcc/testsuite/gcc.target/gcn/cond_smin_1.c | 2 --
gcc/testsuite/gcc.target/gcn/cond_umax_1.c | 2 --
gcc/testsuite/gcc.target/gcn/cond_umin_1.c | 2 --
20 files changed, 81 insertions(+), 65 deletions(-)
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
index 8ad968c339f..61c0798b30d 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
#include <stdint.h>
@@ -29,6 +29,8 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
+
+/* { dg-final { scan-assembler-times {smaxv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3_exec} 3 } } */
+
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
index a801778355a..3d25ffcfe94 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
#include <stdint.h>
@@ -29,7 +29,7 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
+/* { dg-final { scan-assembler-times {smaxv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3_exec} 3 } } */
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
index 002754819ad..55543fec4b0 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
#include <stdint.h>
@@ -29,6 +29,9 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
+/* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
+/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
+/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
index 867b459e0db..65fc2a9b30d 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
#include <stdint.h>
@@ -29,6 +29,9 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
+/* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
+/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
+/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
index 1fd7815e5f8..a4d7ab991de 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
@@ -1,8 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -dp" } */
#include "cond_fmaxnm_1.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
+/* { dg-final { scan-assembler-times {smaxv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3_exec} 3 } } */
+
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
index 4ec60d3a90b..6c64a01bcbb 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
@@ -1,8 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -dp" } */
#include "cond_fmaxnm_2.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
+/* { dg-final { scan-assembler-times {smaxv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3_exec} 3 } } */
+
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
index 6c71a836140..bdb3f2f99ef 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
@@ -1,8 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -dp" } */
#include "cond_fmaxnm_3.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
+/* { dg-final { scan-assembler-times {smaxv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3_exec} 3 } } */
+
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
index 80e287b87b9..c11633b5236 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
@@ -1,8 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -dp" } */
#include "cond_fmaxnm_4.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
+/* { dg-final { scan-assembler-times {smaxv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3_exec} 3 } } */
+
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
index cfb12c0a502..bb456887568 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_1.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
+/* { dg-final { scan-assembler-times {sminv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3_exec} 3 } } */
+
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
index 5c6c333ab6d..502f8987494 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_2.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
+/* { dg-final { scan-assembler-times {sminv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3_exec} 3 } } */
+
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
index b13eabb73d2..2ea1eb2ec2c 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
@@ -1,9 +1,12 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_3.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
+/* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
+/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
+/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
index 2a03bf97a2d..3673ecafc2d 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
@@ -1,9 +1,12 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_4.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
+/* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
+/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
+/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
index cf15929e26e..ac98941a373 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -dp" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_1.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
+/* { dg-final { scan-assembler-times {sminv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3_exec} 3 } } */
+
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
index 0a46fe281a6..7f4dba0d314 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -dp" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_2.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
+/* { dg-final { scan-assembler-times {sminv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3_exec} 3 } } */
+
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
index 679ae18e50e..5faf0c5cc59 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -dp" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_3.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
+/* { dg-final { scan-assembler-times {sminv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3_exec} 3 } } */
+
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
index 2d6a217429d..89d93ac596a 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -dp" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_4.c"
-/* { dg-final { scan-assembler-times {\ts_mov_b64\texec, 1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_..} 36 } } */
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
+/* { dg-final { scan-assembler-times {sminv64sf3_exec} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3_exec} 3 } } */
+
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
index 3460d5c7b98..1a97aba80cd 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
@@ -46,11 +46,9 @@ TEST_ALL(DO_REGREG_OPS, DO_IMMEDIATE_OPS)
/* { dg-final { scan-assembler-times {smaxv64si3_exec} 30 } } */
/* { dg-final { scan-assembler-not {smaxv64si3/0} } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_??} 240 } } */
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_??, 0} } } */
/* { dg-final { scan-assembler-times {\tv_cmp_gt_i32\tvcc, s[0-9]+, v[0-9]+} 80 } } */
/* { dg-final { scan-assembler-not {\tv_cmpx_gt_i32\tvcc, s[0-9]+, v[0-9]+} } } */
/* { dg-final { scan-assembler-not {\ts_cmpk_lg_u32\tvcc_lo, 0} } } */
-/* { dg-final { scan-assembler-times {vec_cmpv64didi_exec} 11 } } */
/* { dg-final { scan-assembler-times {\tv_cmp_ne_u64\ts\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -1} 10 } } */
/* { dg-final { scan-assembler-times {\tv_cmp_gt_i64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 10 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
index b19b6da5960..5050a31ecb4 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
@@ -44,11 +44,9 @@ TEST_ALL (DO_REGREG_OPS, DO_IMMEDIATE_OPS)
/* { dg-final { scan-assembler-times {sminv64si3_exec} 30 } } */
/* { dg-final { scan-assembler-not {sminv64si3/0} } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_??} 240 } } */
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_??, 0} } } */
/* { dg-final { scan-assembler-times {\tv_cmp_gt_i32\tvcc, s[0-9]+, v[0-9]+} 80 } } */
/* { dg-final { scan-assembler-not {\tv_cmpx_gt_i32\tvcc, s[0-9]+, v[0-9]+} } } */
/* { dg-final { scan-assembler-not {\ts_cmpk_lg_u32\tvcc_lo, 0} } } */
-/* { dg-final { scan-assembler-times {vec_cmpv64didi_exec} 11 } } */
/* { dg-final { scan-assembler-times {\tv_cmp_ne_u64\ts\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -1} 10 } } */
/* { dg-final { scan-assembler-times {\tv_cmp_lt_i64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 10 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
index a2d48a5bcef..7f6498b3341 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
@@ -41,11 +41,9 @@ TEST_ALL (DO_REGREG_OPS, DO_IMMEDIATE_OPS)
/* { dg-final { scan-assembler-times {umaxv64si3_exec} 20 } } */
/* { dg-final { scan-assembler-not {umaxv64si3/0} } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_??} 168 } } */
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_??, 0} } } */
/* { dg-final { scan-assembler-times {\tv_cmp_gt_i32\tvcc, s[0-9]+, v[0-9]+} 56 } } */
/* { dg-final { scan-assembler-not {\ts_cmpk_lg_u32\tvcc_lo, 0} } } */
-/* { dg-final { scan-assembler-times {vec_cmpv64didi_exec} 9 } } */
/* { dg-final { scan-assembler-times {\tv_cmp_ne_u64\ts\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], 1} 8 } } */
/* { dg-final { scan-assembler-times {\tv_cmp_gt_u64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 8 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
index f0b7a2d78dd..698aa88fec2 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
@@ -41,10 +41,8 @@ TEST_ALL (DO_REGREG_OPS, DO_IMMEDIATE_OPS)
/* { dg-final { scan-assembler-times {uminv64si3_exec} 20 } } */
/* { dg-final { scan-assembler-not {uminv64si3/0} } } */
-/* { dg-final { scan-assembler-times {\ts_mov_b32\ts[0-9]+, vcc_??} 168 } } */
/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_??, 0} } } */
/* { dg-final { scan-assembler-times {\tv_cmp_gt_i32\tvcc, s[0-9]+, v[0-9]+} 56 } } */
/* { dg-final { scan-assembler-not {\ts_cmpk_lg_u32\tvcc_lo, 0} } } */
-/* { dg-final { scan-assembler-times {vec_cmpv64didi_exec} 9 } } */
/* { dg-final { scan-assembler-times {\tv_cmp_ne_u64\ts\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], 1} 8 } } */
/* { dg-final { scan-assembler-times {\tv_cmp_lt_u64\tvcc, v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]} 8 } } */
reply other threads:[~2023-03-01 14:17 UTC|newest]
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