From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id B140D3858D37; Thu, 2 Mar 2023 23:48:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B140D3858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1677800919; bh=2yyZg1dtBxUqf2KhGlG0MIitLNy4KIPCWhxdyaD+EyE=; h=From:To:Subject:Date:From; b=ZqJ1v4/kLkMUSg0AM6i5z12m1YVnTQSCESBn+I7GLyyjDMk6kv/jPlz1n4w7Fgma7 VLZBM6B5UgarGVr36meYVpQUq2BBeVsLvAG7J3XNY0AjsTkIUpmyheBKW3lMi/J/Cs DlZIxd1MpCBQjJI1SdV1WRdQbcWAV12rmFs7xcDQ= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf009)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf009 X-Git-Oldrev: 340157643fef5828ff5e53697c6daf8ba36fc602 X-Git-Newrev: f6abe0be8958d3aacf080037613682924f188a18 Message-Id: <20230302234839.B140D3858D37@sourceware.org> Date: Thu, 2 Mar 2023 23:48:39 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f6abe0be8958d3aacf080037613682924f188a18 commit f6abe0be8958d3aacf080037613682924f188a18 Author: Michael Meissner Date: Thu Mar 2 18:48:36 2023 -0500 Revert patches Diff: --- gcc/config/rs6000/rs6000.md | 52 --------------------------------------------- 1 file changed, 52 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d23045590c7..ddb8a6abfca 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -996,58 +996,6 @@ (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_insn_and_split "zero_extendditi2" - [(set (match_operand:TI 0 "gpc_reg_operand" "=r,r,wa,wa,wa") - (zero_extend:TI - (match_operand:DI 1 "reg_or_mem_operand" "r,m,b,Z,wa"))) - (clobber (match_scratch:DI 2 "=&X,X,X,X,wa"))] - "TARGET_POWERPC64 && TARGET_P9_VECTOR" - "@ - # - # - mtvsrdd %x0,0,%1 - lxvrdx %x0,%y1 - #" - "&& reload_completed - && (int_reg_operand (operands[0], TImode) - || (vsx_register_operand (operands[0], TImode) - && vsx_register_operand (operands[1], DImode)))" - [(set (match_dup 2) (match_dup 1)) - (set (match_dup 3) (const_int 0))] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - - /* If we are converting a VSX DImode to VSX TImode, we need to move the upper - 64-bits (DImode) to the lower 64-bits. We can't just do a xxpermdi - instruction to swap the two 64-bit words, because can't rely on the bottom - 64-bits of the VSX register being 0. Instead we create a 0 and do the - xxpermdi operation to combine the two registers. */ - if (vsx_register_operand (dest, TImode) - && vsx_register_operand (src, DImode)) - { - rtx tmp = operands[2]; - emit_move_insn (tmp, const0_rtx); - - rtx hi = tmp; - rtx lo = src; - if (!BYTES_BIG_ENDIAN) - std::swap (hi, lo); - - rtx dest_v2di = gen_rtx_REG (V2DImode, reg_or_subregno (dest)); - emit_insn (gen_vsx_concat_v2di (dest_v2di, hi, lo)); - DONE; - } - - /* If we are zero extending to a GPR register either from a GPR register, - a VSX register or from memory, do the zero extend operation to the - lower DI register, and set the upper DI register to 0. */ - operands[2] = gen_lowpart (DImode, dest); - operands[3] = gen_highpart (DImode, dest); -} - [(set_attr "type" "*,load,vecexts,vecload,vecperm") - (set_attr "isa" "*,*,p9v,p10,*") - (set_attr "length" "8,8,*,*,8")]) (define_insn "extendqi2" [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")