From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id B5EEC3858D39; Mon, 13 Mar 2023 16:26:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B5EEC3858D39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1678724768; bh=LFU4Ydtw6HIyoYfBh7zFWKAS3mHvnHkGBLFQ98w09iI=; h=From:To:Subject:Date:From; b=RMkSfWgjPQacfYRQowYDCdmpQFqgRJ6GgbAhwtxmDzW7GwnXsQ4DGN2dot8V5/OaI y60mNTz05tPgaQj6Ugc34whopOs0cIW3EIW7TiQpHiDHTRRwKBz1nqnmOo8DcH1Gbm EstpVCm0F3/+6Ozx9fcXk9STmHofAVu7zMpqC1hM= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-6637] RISC-V: Fine tunning merge operand constraint X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 9dd51550b7d140f5fcc60f892cf68b59ff667b66 X-Git-Newrev: 2219aed9ad6f2678eac457b7de0984dbcde18679 Message-Id: <20230313162608.B5EEC3858D39@sourceware.org> Date: Mon, 13 Mar 2023 16:26:08 +0000 (GMT) List-Id: https://gcc.gnu.org/g:2219aed9ad6f2678eac457b7de0984dbcde18679 commit r13-6637-g2219aed9ad6f2678eac457b7de0984dbcde18679 Author: Ju-Zhe Zhong Date: Wed Mar 8 14:16:21 2023 +0800 RISC-V: Fine tunning merge operand constraint gcc/ChangeLog: * config/riscv/vector-iterators.md (=vd,vr): Fine tune. (=vd,vd,vr,vr): Ditto. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/merge_constraint-2.c: New test. Diff: --- gcc/config/riscv/vector-iterators.md | 6 +- gcc/config/riscv/vector.md | 890 ++++++++++----------- .../gcc.target/riscv/rvv/base/merge_constraint-2.c | 118 +++ 3 files changed, 566 insertions(+), 448 deletions(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index d44943ae7c3..266563a3aa0 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -813,9 +813,9 @@ (UNSPEC_VSLIDE1UP "1up") (UNSPEC_VSLIDE1DOWN "1down") (UNSPEC_VFSLIDE1UP "1up") (UNSPEC_VFSLIDE1DOWN "1down")]) -(define_int_attr ud_constraint [(UNSPEC_VSLIDEUP "=&vr,&vr") (UNSPEC_VSLIDEDOWN "=vd,vr") - (UNSPEC_VSLIDE1UP "=&vr,&vr") (UNSPEC_VSLIDE1DOWN "=vd,vr") - (UNSPEC_VFSLIDE1UP "=&vr,&vr") (UNSPEC_VFSLIDE1DOWN "=vd,vr")]) +(define_int_attr ud_constraint [(UNSPEC_VSLIDEUP "=&vr,&vr,&vr,&vr") (UNSPEC_VSLIDEDOWN "=vd,vd,vr,vr") + (UNSPEC_VSLIDE1UP "=&vr,&vr,&vr,&vr") (UNSPEC_VSLIDE1DOWN "=vd,vd,vr,vr") + (UNSPEC_VFSLIDE1UP "=&vr,&vr,&vr,&vr") (UNSPEC_VFSLIDE1DOWN "=vd,vd,vr,vr")]) (define_int_attr UNSPEC [(UNSPEC_VSLIDE1UP "UNSPEC_VSLIDE1UP") (UNSPEC_VSLIDE1DOWN "UNSPEC_VSLIDE1DOWN")]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 178d2950493..977d3f2042c 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4653,123 +4653,123 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_mul_plus" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rK") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (any_extend:VWEXTI - (match_operand: 3 "register_operand" " vr")) + (match_operand: 3 "register_operand" " vr, vr")) (any_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) - (match_operand:VWEXTI 5 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0")) + (match_operand:VWEXTI 5 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vwmacc.vv\t%0,%3,%4%p1" [(set_attr "type" "viwmuladd") (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plus_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rK") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (any_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "register_operand" " r"))) + (match_operand: 3 "register_operand" " r, r"))) (any_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) - (match_operand:VWEXTI 5 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0")) + (match_operand:VWEXTI 5 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vwmacc.vx\t%0,%3,%4%p1" [(set_attr "type" "viwmuladd") (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plussu" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rK") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (sign_extend:VWEXTI - (match_operand: 3 "register_operand" " vr")) + (match_operand: 3 "register_operand" " vr, vr")) (zero_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) - (match_operand:VWEXTI 5 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0")) + (match_operand:VWEXTI 5 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vwmaccsu.vv\t%0,%3,%4%p1" [(set_attr "type" "viwmuladd") (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plussu_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rK") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (sign_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "register_operand" " r"))) + (match_operand: 3 "register_operand" " r, r"))) (zero_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) - (match_operand:VWEXTI 5 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0")) + (match_operand:VWEXTI 5 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vwmaccsu.vx\t%0,%3,%4%p1" [(set_attr "type" "viwmuladd") (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plusus_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rK") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (zero_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "register_operand" " r"))) + (match_operand: 3 "register_operand" " r, r"))) (sign_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) - (match_operand:VWEXTI 5 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0")) + (match_operand:VWEXTI 5 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vwmaccus.vx\t%0,%3,%4%p1" [(set_attr "type" "viwmuladd") @@ -4908,55 +4908,55 @@ (set_attr "mode" "")]) (define_insn "@pred_" - [(set (match_operand:VB 0 "register_operand" "=&vr") + [(set (match_operand:VB 0 "register_operand" "=&vr, &vr") (if_then_else:VB (unspec:VB - [(match_operand:VB 1 "vector_mask_operand" "vmWc1") - (match_operand 4 "vector_length_operand" " rK") - (match_operand 5 "const_int_operand" " i") - (match_operand 6 "const_int_operand" " i") + [(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VB - [(match_operand:VB 3 "register_operand" " vr")] VMISC) - (match_operand:VB 2 "vector_merge_operand" " 0vu")))] + [(match_operand:VB 3 "register_operand" " vr, vr")] VMISC) + (match_operand:VB 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vm.m\t%0,%3%p1" [(set_attr "type" "vmsfs") (set_attr "mode" "")]) (define_insn "@pred_iota" - [(set (match_operand:VI 0 "register_operand" "=&vr") + [(set (match_operand:VI 0 "register_operand" "=&vr, &vr") (if_then_else:VI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 4 "vector_length_operand" " rK") - (match_operand 5 "const_int_operand" " i") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VI - [(match_operand: 3 "register_operand" " vr")] UNSPEC_VIOTA) - (match_operand:VI 2 "vector_merge_operand" " 0vu")))] + [(match_operand: 3 "register_operand" " vr, vr")] UNSPEC_VIOTA) + (match_operand:VI 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "viota.m\t%0,%3%p1" [(set_attr "type" "vmiota") (set_attr "mode" "")]) (define_insn "@pred_series" - [(set (match_operand:VI 0 "register_operand" "=vd, vr") + [(set (match_operand:VI 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 3 "vector_length_operand" " rK, rK") - (match_operand 4 "const_int_operand" " i, i") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 3 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 4 "const_int_operand" " i, i, i, i") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (vec_series:VI (const_int 0) (const_int 1)) - (match_operand:VI 2 "vector_merge_operand" "0vu,0vu")))] + (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vid.v\t%0%p1" [(set_attr "type" "vmidx") @@ -4973,124 +4973,124 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vr") + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float_binop:VF - (match_operand:VF 3 "register_operand" " vr, vr") - (match_operand:VF 4 "register_operand" " vr, vr")) - (match_operand:VF 2 "vector_merge_operand" "0vu,0vu")))] + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") + (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.vv\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) (define_insn "@pred__scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, vr") + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (commutative_float_binop:VF (vec_duplicate:VF - (match_operand: 4 "register_operand" " f, f")) - (match_operand:VF 3 "register_operand" " vr, vr")) - (match_operand:VF 2 "vector_merge_operand" "0vu,0vu")))] + (match_operand: 4 "register_operand" " f, f, f, f")) + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.vf\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) (define_insn "@pred__scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, vr") + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (non_commutative_float_binop:VF - (match_operand:VF 3 "register_operand" " vr, vr") + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") (vec_duplicate:VF - (match_operand: 4 "register_operand" " f, f"))) - (match_operand:VF 2 "vector_merge_operand" "0vu,0vu")))] + (match_operand: 4 "register_operand" " f, f, f, f"))) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.vf\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) (define_insn "@pred__reverse_scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, vr") + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (non_commutative_float_binop:VF (vec_duplicate:VF - (match_operand: 4 "register_operand" " f, f")) - (match_operand:VF 3 "register_operand" " vr, vr")) - (match_operand:VF 2 "vector_merge_operand" "0vu,0vu")))] + (match_operand: 4 "register_operand" " f, f, f, f")) + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfr.vf\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vr") + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VF - [(match_operand:VF 3 "register_operand" " vr, vr") - (match_operand:VF 4 "register_operand" " vr, vr")] VCOPYSIGNS) - (match_operand:VF 2 "vector_merge_operand" "0vu,0vu")))] + [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr") + (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfsgnj.vv\t%0,%3,%4%p1" [(set_attr "type" "vfsgnj") (set_attr "mode" "")]) (define_insn "@pred__scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, vr") + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VF - [(match_operand:VF 3 "register_operand" " vr, vr") - (vec_duplicate:VF - (match_operand: 4 "register_operand" " f, f"))] VCOPYSIGNS) - (match_operand:VF 2 "vector_merge_operand" "0vu,0vu")))] + [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr") + (vec_duplicate:VF + (match_operand: 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfsgnj.vf\t%0,%3,%4%p1" [(set_attr "type" "vfsgnj") @@ -5711,19 +5711,19 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vr") + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float_unop:VF - (match_operand:VF 3 "register_operand" " vr, vr")) - (match_operand:VF 2 "vector_merge_operand" "0vu,0vu")))] + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.v\t%0,%3%p1" [(set_attr "type" "") @@ -5734,38 +5734,38 @@ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))]) (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vr") + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VF - [(match_operand:VF 3 "register_operand" " vr, vr")] VFMISC) - (match_operand:VF 2 "vector_merge_operand" "0vu,0vu")))] + [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.v\t%0,%3%p1" [(set_attr "type" "") (set_attr "mode" "")]) (define_insn "@pred_class" - [(set (match_operand: 0 "register_operand" "=vd, vr") + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec: - [(match_operand:VF 3 "register_operand" " vr, vr")] UNSPEC_VFCLASS) - (match_operand: 2 "vector_merge_operand" "0vu,0vu")))] + [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfclass.v\t%0,%3%p1" [(set_attr "type" "vfclass") @@ -5781,88 +5781,88 @@ ;; Vector Widening Add/Subtract/Multiply. (define_insn "@pred_dual_widen_" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTF (float_extend:VWEXTF - (match_operand: 3 "register_operand" " vr")) + (match_operand: 3 "register_operand" " vr, vr")) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTF 2 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr"))) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vf") (set_attr "mode" "")]) (define_insn "@pred_dual_widen__scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTF (float_extend:VWEXTF - (match_operand: 3 "register_operand" " vr")) + (match_operand: 3 "register_operand" " vr, vr")) (float_extend:VWEXTF (vec_duplicate: - (match_operand: 4 "register_operand" " f")))) - (match_operand:VWEXTF 2 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " f, f")))) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vf") (set_attr "mode" "")]) (define_insn "@pred_single_widen_" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF - (match_operand:VWEXTF 3 "register_operand" " vr") + (match_operand:VWEXTF 3 "register_operand" " vr, vr") (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTF 2 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr"))) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfw.wv\t%0,%3,%4%p1" [(set_attr "type" "vf") (set_attr "mode" "")]) (define_insn "@pred_single_widen__scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF - (match_operand:VWEXTF 3 "register_operand" " vr") + (match_operand:VWEXTF 3 "register_operand" " vr, vr") (float_extend:VWEXTF (vec_duplicate: - (match_operand: 4 "register_operand" " f")))) - (match_operand:VWEXTF 2 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " f, f")))) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfw.wf\t%0,%3,%4%p1" [(set_attr "type" "vf") @@ -5876,100 +5876,100 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_mul_" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rK") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") + (match_operand:VWEXTF 2 "register_operand" " 0, 0") (mult:VWEXTF (float_extend:VWEXTF - (match_operand: 3 "register_operand" " vr")) + (match_operand: 3 "register_operand" " vr, vr")) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr")))) - (match_operand:VWEXTF 5 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr")))) + (match_operand:VWEXTF 5 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) (define_insn "@pred_widen_mul__scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rK") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") + (match_operand:VWEXTF 2 "register_operand" " 0, 0") (mult:VWEXTF (float_extend:VWEXTF (vec_duplicate: - (match_operand: 3 "register_operand" " f"))) + (match_operand: 3 "register_operand" " f, f"))) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr")))) - (match_operand:VWEXTF 5 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr")))) + (match_operand:VWEXTF 5 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) (define_insn "@pred_widen_neg_mul_" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rK") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (neg:VWEXTF (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") + (match_operand:VWEXTF 2 "register_operand" " 0, 0") (mult:VWEXTF (float_extend:VWEXTF - (match_operand: 3 "register_operand" " vr")) + (match_operand: 3 "register_operand" " vr, vr")) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr"))))) - (match_operand:VWEXTF 5 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr"))))) + (match_operand:VWEXTF 5 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) (define_insn "@pred_widen_neg_mul__scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rK") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (neg:VWEXTF (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") + (match_operand:VWEXTF 2 "register_operand" " 0, 0") (mult:VWEXTF (float_extend:VWEXTF (vec_duplicate: - (match_operand: 3 "register_operand" " f"))) + (match_operand: 3 "register_operand" " f, f"))) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr"))))) - (match_operand:VWEXTF 5 "vector_merge_operand" " 0vu")))] + (match_operand: 4 "register_operand" " vr, vr"))))) + (match_operand:VWEXTF 5 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") @@ -6167,21 +6167,21 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_merge_scalar" - [(set (match_operand:VF 0 "register_operand" "=vd") + [(set (match_operand:VF 0 "register_operand" "=vd,vd") (if_then_else:VF - (match_operand: 4 "register_operand" " vm") + (match_operand: 4 "register_operand" " vm,vm") (if_then_else:VF (unspec: [(match_dup 4) - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") + (match_operand 5 "vector_length_operand" " rK,rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (vec_duplicate:VF - (match_operand: 3 "register_operand" " f")) - (match_operand:VF 2 "register_operand" " vr")) - (match_operand:VF 1 "vector_merge_operand" "0vu")))] + (match_operand: 3 "register_operand" " f, f")) + (match_operand:VF 2 "register_operand" " vr,vr")) + (match_operand:VF 1 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfmerge.vfm\t%0,%2,%3,%4" [(set_attr "type" "vfmerge") @@ -6195,57 +6195,57 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_fcvt_x_f" - [(set (match_operand: 0 "register_operand" "=vd, vr") + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec: - [(match_operand:VF 3 "register_operand" " vr, vr")] VFCVTS) - (match_operand: 2 "vector_merge_operand" "0vu,0vu")))] + [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfcvt.x.f.v\t%0,%3%p1" [(set_attr "type" "vfcvtftoi") (set_attr "mode" "")]) (define_insn "@pred_" - [(set (match_operand: 0 "register_operand" "=vd, vr") + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix: - (match_operand:VF 3 "register_operand" " vr, vr")) - (match_operand: 2 "vector_merge_operand" "0vu,0vu")))] + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfcvt.rtz.x.f.v\t%0,%3%p1" [(set_attr "type" "vfcvtftoi") (set_attr "mode" "")]) (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vr") + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float:VF - (match_operand: 3 "register_operand" " vr, vr")) - (match_operand:VF 2 "vector_merge_operand" "0vu,0vu")))] + (match_operand: 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfcvt.f.x.v\t%0,%3%p1" [(set_attr "type" "vfcvtitof") @@ -6259,76 +6259,76 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_fcvt_x_f" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWCONVERTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 4 "vector_length_operand" " rK") - (match_operand 5 "const_int_operand" " i") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VWCONVERTI - [(match_operand: 3 "register_operand" " vr")] VFCVTS) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " 0vu")))] + [(match_operand: 3 "register_operand" " vr, vr")] VFCVTS) + (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.x.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") (set_attr "mode" "")]) (define_insn "@pred_widen_" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWCONVERTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 4 "vector_length_operand" " rK") - (match_operand 5 "const_int_operand" " i") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:VWCONVERTI - (match_operand: 3 "register_operand" " vr")) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " 0vu")))] + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.rtz.x.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") (set_attr "mode" "")]) (define_insn "@pred_widen_" - [(set (match_operand:VF 0 "register_operand" "=&vr") + [(set (match_operand:VF 0 "register_operand" "=&vr, &vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 4 "vector_length_operand" " rK") - (match_operand 5 "const_int_operand" " i") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float:VF - (match_operand: 3 "register_operand" " vr")) - (match_operand:VF 2 "vector_merge_operand" " 0vu")))] + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:VF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.x.v\t%0,%3%p1" [(set_attr "type" "vfwcvtitof") (set_attr "mode" "")]) (define_insn "@pred_extend" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 4 "vector_length_operand" " rK") - (match_operand 5 "const_int_operand" " i") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (float_extend:VWEXTF - (match_operand: 3 "register_operand" " vr")) - (match_operand:VWEXTF 2 "vector_merge_operand" " 0vu")))] + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftof") @@ -6454,189 +6454,189 @@ ;; For example, The LMUL = 1 corresponding mode of VNx16QImode is VNx4QImode ;; for -march=rv*zve32* wheras VNx8QImode for -march=rv*zve64* (define_insn "@pred_reduc_" - [(set (match_operand: 0 "register_operand" "=vd, vr") + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_reduc:VI (vec_duplicate:VI (vec_select: - (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr, vr, vr") (parallel [(const_int 0)]))) - (match_operand:VI 3 "register_operand" " vr, vr")) - (match_operand: 2 "vector_merge_operand" "0vu,0vu")] UNSPEC_REDUC))] + (match_operand:VI 3 "register_operand" " vr, vr, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN > 32" "vred.vs\t%0,%3,%4%p1" [(set_attr "type" "vired") (set_attr "mode" "")]) (define_insn "@pred_reduc_" - [(set (match_operand: 0 "register_operand" "=vd, vr") + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_reduc:VI_ZVE32 (vec_duplicate:VI_ZVE32 (vec_select: - (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr, vr, vr") (parallel [(const_int 0)]))) - (match_operand:VI_ZVE32 3 "register_operand" " vr, vr")) - (match_operand: 2 "vector_merge_operand" "0vu,0vu")] UNSPEC_REDUC))] + (match_operand:VI_ZVE32 3 "register_operand" " vr, vr, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN == 32" "vred.vs\t%0,%3,%4%p1" [(set_attr "type" "vired") (set_attr "mode" "")]) (define_insn "@pred_widen_reduc_plus" - [(set (match_operand: 0 "register_operand" "=&vr") + [(set (match_operand: 0 "register_operand" "=&vr, &vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VWI 3 "register_operand" " vr") - (match_operand: 4 "register_operand" " vr") - (match_operand: 2 "vector_merge_operand" " 0vu")] WREDUC))] + (match_operand:VWI 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 2 "vector_merge_operand" " vu, 0")] WREDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN > 32" "vwredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "viwred") (set_attr "mode" "")]) (define_insn "@pred_widen_reduc_plus" - [(set (match_operand: 0 "register_operand" "=&vr") + [(set (match_operand: 0 "register_operand" "=&vr, &vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VWI_ZVE32 3 "register_operand" " vr") - (match_operand: 4 "register_operand" " vr") - (match_operand: 2 "vector_merge_operand" " 0vu")] WREDUC))] + (match_operand:VWI_ZVE32 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 2 "vector_merge_operand" " vu, 0")] WREDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN == 32" "vwredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "viwred") (set_attr "mode" "")]) (define_insn "@pred_reduc_" - [(set (match_operand: 0 "register_operand" "=vd, vr") + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_freduc:VF (vec_duplicate:VF (vec_select: - (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr, vr, vr") (parallel [(const_int 0)]))) - (match_operand:VF 3 "register_operand" " vr, vr")) - (match_operand: 2 "vector_merge_operand" "0vu,0vu")] UNSPEC_REDUC))] + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN > 32" "vfred.vs\t%0,%3,%4%p1" [(set_attr "type" "vfredu") (set_attr "mode" "")]) (define_insn "@pred_reduc_" - [(set (match_operand: 0 "register_operand" "=vd, vr") + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_freduc:VF_ZVE32 (vec_duplicate:VF_ZVE32 (vec_select: - (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr, vr, vr") (parallel [(const_int 0)]))) - (match_operand:VF_ZVE32 3 "register_operand" " vr, vr")) - (match_operand: 2 "vector_merge_operand" "0vu,0vu")] UNSPEC_REDUC))] + (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN == 32" "vfred.vs\t%0,%3,%4%p1" [(set_attr "type" "vfredu") (set_attr "mode" "")]) (define_insn "@pred_reduc_plus" - [(set (match_operand: 0 "register_operand" "=vd, vr") + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (unspec: [(unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VF (vec_duplicate:VF (vec_select: - (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr, vr, vr") (parallel [(const_int 0)]))) - (match_operand:VF 3 "register_operand" " vr, vr")) - (match_operand: 2 "vector_merge_operand" "0vu,0vu")] UNSPEC_REDUC)] ORDER))] + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))] "TARGET_VECTOR && TARGET_MIN_VLEN > 32" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") (set_attr "mode" "")]) (define_insn "@pred_reduc_plus" - [(set (match_operand: 0 "register_operand" "=vd, vr") + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (unspec: [(unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VF_ZVE32 (vec_duplicate:VF_ZVE32 (vec_select: - (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr, vr, vr") (parallel [(const_int 0)]))) - (match_operand:VF_ZVE32 3 "register_operand" " vr, vr")) - (match_operand: 2 "vector_merge_operand" "0vu,0vu")] UNSPEC_REDUC)] ORDER))] + (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))] "TARGET_VECTOR && TARGET_MIN_VLEN == 32" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") (set_attr "mode" "")]) (define_insn "@pred_widen_reduc_plus" - [(set (match_operand: 0 "register_operand" "=&vr") + [(set (match_operand: 0 "register_operand" "=&vr, &vr") (unspec: [(unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VWF 3 "register_operand" " vr") - (match_operand: 4 "register_operand" " vr") - (match_operand: 2 "vector_merge_operand" " 0vu")] UNSPEC_WREDUC_SUM)] ORDER))] + (match_operand:VWF 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] "TARGET_VECTOR && TARGET_MIN_VLEN > 32" "vfwredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfwred") @@ -6750,16 +6750,16 @@ [(set (match_operand:V 0 "register_operand" "") (unspec:V [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:V 2 "vector_merge_operand" " 0vu, 0vu") - (match_operand:V 3 "register_operand" " vr, vr") - (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] VSLIDES))] + (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0") + (match_operand:V 3 "register_operand" " vr, vr, vr, vr") + (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSLIDES))] "TARGET_VECTOR" "vslide.v%o4\t%0,%3,%4%p1" [(set_attr "type" "vslide") @@ -6770,16 +6770,16 @@ [(set (match_operand:VI_QHS 0 "register_operand" "") (unspec:VI_QHS [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VI_QHS 2 "vector_merge_operand" " 0vu, 0vu") - (match_operand:VI_QHS 3 "register_operand" " vr, vr") - (match_operand: 4 "reg_or_0_operand" " rJ, rJ")] VSLIDES1))] + (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0") + (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr") + (match_operand: 4 "reg_or_0_operand" " rK, rK, rK, rK")] VSLIDES1))] "TARGET_VECTOR" "vslide.vx\t%0,%3,%z4%p1" [(set_attr "type" "vislide") @@ -6811,16 +6811,16 @@ [(set (match_operand:VI_D 0 "register_operand" "") (unspec:VI_D [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VI_D 2 "vector_merge_operand" " 0vu, 0vu") - (match_operand:VI_D 3 "register_operand" " vr, vr") - (match_operand: 4 "reg_or_0_operand" " rJ, rJ")] VSLIDES1))] + (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0") + (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") + (match_operand: 4 "reg_or_0_operand" " rK, rK, rK, rK")] VSLIDES1))] "TARGET_VECTOR" "vslide.vx\t%0,%3,%z4%p1" [(set_attr "type" "vislide") @@ -6830,17 +6830,17 @@ [(set (match_operand:VI_D 0 "register_operand" "") (unspec:VI_D [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VI_D 2 "vector_merge_operand" " 0vu, 0vu") - (match_operand:VI_D 3 "register_operand" " vr, vr") + (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0") + (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") (sign_extend: - (match_operand: 4 "reg_or_0_operand" " rJ, rJ"))] VSLIDES1))] + (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))] "TARGET_VECTOR" "vslide.vx\t%0,%3,%z4%p1" [(set_attr "type" "vislide") @@ -6851,16 +6851,16 @@ [(set (match_operand:VF 0 "register_operand" "") (unspec:VF [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VF 2 "vector_merge_operand" " 0vu, 0vu") - (match_operand:VF 3 "register_operand" " vr, vr") - (match_operand: 4 "register_operand" " f, f")] VFSLIDES1))] + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0") + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") + (match_operand: 4 "register_operand" " f, f, f, f")] VFSLIDES1))] "TARGET_VECTOR" "vfslide.vf\t%0,%3,%4%p1" [(set_attr "type" "vfslide") @@ -6868,40 +6868,40 @@ ;; vrgather (define_insn "@pred_gather" - [(set (match_operand:V 0 "register_operand" "=&vr") + [(set (match_operand:V 0 "register_operand" "=&vr, &vr") (if_then_else:V (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:V - [(match_operand:V 3 "register_operand" " vr") - (match_operand: 4 "register_operand" " vr")] UNSPEC_VRGATHER) - (match_operand:V 2 "vector_merge_operand" " 0vu")))] + [(match_operand:V 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr")] UNSPEC_VRGATHER) + (match_operand:V 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vrgather.vv\t%0,%3,%4%p1" [(set_attr "type" "vgather") (set_attr "mode" "")]) (define_insn "@pred_gather_scalar" - [(set (match_operand:V 0 "register_operand" "=&vr") + [(set (match_operand:V 0 "register_operand" "=&vr, &vr") (if_then_else:V (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:V - [(match_operand:V 3 "register_operand" " vr") - (match_operand 4 "pmode_reg_or_uimm5_operand" " rK")] UNSPEC_VRGATHER) - (match_operand:V 2 "vector_merge_operand" " 0vu")))] + [(match_operand:V 3 "register_operand" " vr, vr") + (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] UNSPEC_VRGATHER) + (match_operand:V 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vrgather.v%o4\t%0,%3,%4%p1" [(set_attr "type" "vgather") @@ -6909,20 +6909,20 @@ ;; vrgatherei16 (define_insn "@pred_gatherei16" - [(set (match_operand:VEI16 0 "register_operand" "=&vr") + [(set (match_operand:VEI16 0 "register_operand" "=&vr, &vr") (if_then_else:VEI16 (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEI16 - [(match_operand:VEI16 3 "register_operand" " vr") - (match_operand: 4 "register_operand" " vr")] UNSPEC_VRGATHEREI16) - (match_operand:VEI16 2 "vector_merge_operand" " 0vu")))] + [(match_operand:VEI16 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr")] UNSPEC_VRGATHEREI16) + (match_operand:VEI16 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vrgatherei16.vv\t%0,%3,%4%p1" [(set_attr "type" "vgather") @@ -6930,17 +6930,17 @@ ;; vcompress (define_insn "@pred_compress" - [(set (match_operand:V 0 "register_operand" "=&vr") + [(set (match_operand:V 0 "register_operand" "=&vr, &vr") (unspec:V [(unspec: - [(match_operand: 3 "register_operand" " vm") - (match_operand 4 "vector_length_operand" " rK") - (match_operand 5 "const_int_operand" " i") - (match_operand 6 "const_int_operand" " i") + [(match_operand: 3 "register_operand" " vm, vm") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:V 2 "register_operand" " vr") - (match_operand:V 1 "vector_merge_operand" " 0vu")] UNSPEC_VCOMPRESS))] + (match_operand:V 2 "register_operand" " vr, vr") + (match_operand:V 1 "vector_merge_operand" " vu, 0")] UNSPEC_VCOMPRESS))] "TARGET_VECTOR" "vcompress.vm\t%0,%2,%3" [(set_attr "type" "vcompress") @@ -6970,19 +6970,19 @@ (set_attr "mode" "DI")]) (define_insn "@pred_fault_load" - [(set (match_operand:V 0 "register_operand" "=vd, vr") + [(set (match_operand:V 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:V (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, Wc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm, Wc1, Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:V - [(match_operand:V 3 "memory_operand" " m, m")] UNSPEC_VLEFF) - (match_operand:V 2 "vector_merge_operand" " 0vu, 0vu"))) + [(match_operand:V 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF) + (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0"))) (set (reg:SI VL_REGNUM) (unspec:SI [(match_dup 0)] UNSPEC_VLEFF))] "TARGET_VECTOR" "vleff.v\t%0,%3%p1" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-2.c new file mode 100644 index 00000000000..8d9d5655839 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-2.c @@ -0,0 +1,118 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ + +#include "riscv_vector.h" + +void f0 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfadd_vv_f32m1 (v, v, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +void f1 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfadd_vf_f32m1 (v, 8.9, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +void f2 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfdiv_vv_f32m1 (v, v, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +void f4 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfdiv_vf_f32m1 (v, 8.9, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +void f5 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfrdiv_vf_f32m1 (v, 8.9, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +void f6 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfsgnj_vv_f32m1 (v, v, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +void f7 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfsgnj_vf_f32m1 (v, 8.9, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +void f8 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfsqrt_v_f32m1 (v, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +void f9 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfrec7_v_f32m1 (v, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +void f10 (int8_t* base1,int8_t* base2,int8_t* out,int n) +{ + vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32); + vbool32_t m = __riscv_vlm_v_b32 (base1 + 200, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vmerge_vxm_i8mf4 (v, 100, m, 32); + v = __riscv_vle8_v_i8mf4_tu (v, base2, 32); + } + __riscv_vse8_v_i8mf4 (out, v, 32); +} + +void f11 (void* base1,void* base2,void* out,int n) +{ + vfloat32m1_t v = __riscv_vle32_v_f32m1 (base1, 32); + vbool32_t m = __riscv_vlm_v_b32 (base1 + 200, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vfmerge_vfm_f32m1 (v, 8.9, m, 32); + v = __riscv_vle32_v_f32m1_tu (v, base2, 32); + } + __riscv_vse32_v_f32m1 (out, v, 32); +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */