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From: Kito Cheng <kito@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-6733] RISC-V: Use reg_or_subregno to check regno [PR109092] Date: Fri, 17 Mar 2023 09:50:08 +0000 (GMT) [thread overview] Message-ID: <20230317095008.744F73858410@sourceware.org> (raw) https://gcc.gnu.org/g:02880e7803b19c357718abd2f0d567b4a761f318 commit r13-6733-g02880e7803b19c357718abd2f0d567b4a761f318 Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Date: Mon Mar 13 22:17:57 2023 +0800 RISC-V: Use reg_or_subregno to check regno [PR109092] gcc/ChangeLog: PR target/109092 * config/riscv/riscv.md: Fix subreg bug. Diff: --- gcc/config/riscv/riscv.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 863400cd447..bc384d9aedf 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1369,8 +1369,8 @@ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] "TARGET_64BIT && !TARGET_ZBA - && !(REG_P (operands[1]) - && REGNO (operands[1]) == VL_REGNUM)" + && !(register_operand (operands[1], SImode) + && reg_or_subregno (operands[1]) == VL_REGNUM)" "@ # lwu\t%0,%1" @@ -1752,7 +1752,7 @@ "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && !(register_operand (operands[1], SImode) - && REGNO (operands[1]) == VL_REGNUM)" + && reg_or_subregno (operands[1]) == VL_REGNUM)" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb") (set_attr "mode" "SI")
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