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From: Philipp Tomsich <ptomsich@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r13-6877] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair
Date: Mon, 27 Mar 2023 12:19:04 +0000 (GMT)	[thread overview]
Message-ID: <20230327121904.643A83858D39@sourceware.org> (raw)

https://gcc.gnu.org/g:9da6f93144619b0f798c2b43d7cf4fc8d42c13a0

commit r13-6877-g9da6f93144619b0f798c2b43d7cf4fc8d42c13a0
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date:   Mon Mar 27 12:51:51 2023 +0200

    target/109296 - riscv: Add missing mode specifiers for XTheadMemPair
    
    This patch adds missing mode specifiers for XTheadMemPair INSNs.
    
    gcc/ChangeLog:
            PR target/109296
            * config/riscv/thead.md: Add missing mode specifiers.
    
    Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

Diff:
---
 gcc/config/riscv/thead.md | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 63c4af6f77d..0623607d3dc 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -321,10 +321,10 @@
 
 ;; MEMPAIR load DI extended signed SI
 (define_insn "*th_mempair_load_extendsidi2"
-  [(set (match_operand 0 "register_operand" "=r")
-	(sign_extend:DI (match_operand 1 "memory_operand" "m")))
-   (set (match_operand 2 "register_operand" "=r")
-	(sign_extend:DI (match_operand 3 "memory_operand" "m")))]
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (match_operand:SI 1 "memory_operand" "m")))
+   (set (match_operand:DI 2 "register_operand" "=r")
+	(sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
   "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
    && th_mempair_operands_p (operands, true, SImode)"
   { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); }
@@ -334,10 +334,10 @@
 
 ;; MEMPAIR load DI extended unsigned SI
 (define_insn "*th_mempair_load_zero_extendsidi2"
-  [(set (match_operand 0 "register_operand" "=r")
-	(zero_extend:DI (match_operand 1 "memory_operand" "m")))
-   (set (match_operand 2 "register_operand" "=r")
-	(zero_extend:DI (match_operand 3 "memory_operand" "m")))]
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (match_operand:SI 1 "memory_operand" "m")))
+   (set (match_operand:DI 2 "register_operand" "=r")
+	(zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
   "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
    && th_mempair_operands_p (operands, true, SImode)"
   { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }

                 reply	other threads:[~2023-03-27 12:19 UTC|newest]

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