From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 643A83858D39; Mon, 27 Mar 2023 12:19:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 643A83858D39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1679919544; bh=iCvObEzrFs6O8SxrelRpXVGl9eQQmRJyF80f6l5UrKw=; h=From:To:Subject:Date:From; b=wm/6cK2fJ7IOng/iKJz25TPqTcBTKb0/IcnxMIm5G/PnSqo/i4OnD8MIixihCCko/ GF9XYGIittLUG0r9LXJYlIXq4wmhj2nd1EE5g1PG0ipTe2KilyF0KWoAMXI6fZ6kUZ E7GHHbIMGoWwjfSev2cXqSJl1kr/B77GHmDboxds= MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-6877] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair X-Act-Checkin: gcc X-Git-Author: =?utf-8?q?Christoph_M=C3=BCllner?= X-Git-Refname: refs/heads/master X-Git-Oldrev: 3c0f5a9533bcb200d2d49755e653cf8f6c637118 X-Git-Newrev: 9da6f93144619b0f798c2b43d7cf4fc8d42c13a0 Message-Id: <20230327121904.643A83858D39@sourceware.org> Date: Mon, 27 Mar 2023 12:19:04 +0000 (GMT) List-Id: https://gcc.gnu.org/g:9da6f93144619b0f798c2b43d7cf4fc8d42c13a0 commit r13-6877-g9da6f93144619b0f798c2b43d7cf4fc8d42c13a0 Author: Christoph Müllner Date: Mon Mar 27 12:51:51 2023 +0200 target/109296 - riscv: Add missing mode specifiers for XTheadMemPair This patch adds missing mode specifiers for XTheadMemPair INSNs. gcc/ChangeLog: PR target/109296 * config/riscv/thead.md: Add missing mode specifiers. Signed-off-by: Christoph Müllner Diff: --- gcc/config/riscv/thead.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 63c4af6f77d..0623607d3dc 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -321,10 +321,10 @@ ;; MEMPAIR load DI extended signed SI (define_insn "*th_mempair_load_extendsidi2" - [(set (match_operand 0 "register_operand" "=r") - (sign_extend:DI (match_operand 1 "memory_operand" "m"))) - (set (match_operand 2 "register_operand" "=r") - (sign_extend:DI (match_operand 3 "memory_operand" "m")))] + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (match_operand:SI 1 "memory_operand" "m"))) + (set (match_operand:DI 2 "register_operand" "=r") + (sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))] "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed && th_mempair_operands_p (operands, true, SImode)" { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); } @@ -334,10 +334,10 @@ ;; MEMPAIR load DI extended unsigned SI (define_insn "*th_mempair_load_zero_extendsidi2" - [(set (match_operand 0 "register_operand" "=r") - (zero_extend:DI (match_operand 1 "memory_operand" "m"))) - (set (match_operand 2 "register_operand" "=r") - (zero_extend:DI (match_operand 3 "memory_operand" "m")))] + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (match_operand:SI 1 "memory_operand" "m"))) + (set (match_operand:DI 2 "register_operand" "=r") + (zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))] "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed && th_mempair_operands_p (operands, true, SImode)" { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }