From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 7C0F13858C54; Tue, 28 Mar 2023 20:05:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7C0F13858C54 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680033941; bh=NiYrjt1xMwtV6LxCGWPiSZbfQgkPYd9LjzzPnEqo524=; h=From:To:Subject:Date:From; b=X/PbluWSdG79Hv/7fU+gZt0uhT5+t/5Lu/4nL/GxwwtNM2xGosVLBUonXru1GUmyU 9ZcZcth4v8GzR82WgPh0hYUHBx7WMk6yxT4IlylhfSl+JGL/DP3wB91XlQjm4HcsiR WPa6z6xr1+WJI5uZu/br9hfc132NZPTD87A6mWmg= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work116-dmf)] Update ChangeLog.* X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work116-dmf X-Git-Oldrev: ec28dbf2f6572ebeb1f7da22d8fc42794c060345 X-Git-Newrev: 6a0c8b23dcb9efe2a6d1a1a43d8a23aa72031ce8 Message-Id: <20230328200541.7C0F13858C54@sourceware.org> Date: Tue, 28 Mar 2023 20:05:41 +0000 (GMT) List-Id: https://gcc.gnu.org/g:6a0c8b23dcb9efe2a6d1a1a43d8a23aa72031ce8 commit 6a0c8b23dcb9efe2a6d1a1a43d8a23aa72031ce8 Author: Michael Meissner Date: Fri Mar 24 18:34:48 2023 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index a7adc17c17b..781e30b3a21 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,47 @@ +==================== Branch work116-dmf, patch #1 ==================== + +Make load/cmp fusion know about prefixed loads. + +The issue with the bug is the power10 load GPR + cmpi -1/0/1 fusion +optimization generates illegal assembler code. + +Ultimately the code was dying because the fusion load + compare -1/0/1 patterns +did not handle the possibility that the load might be prefixed. + +The main cause is the constraints for the individual loads in the fusion did not +match the machine. In particular, LWA is a ds format instruction when it is +unprefixed. The code did not also set the prefixed attribute correctly. + +This patch rewrites the genfusion.pl script so that it will have more accurate +constraints for the LWA and LD instructions (which are DS instructions). The +updated genfusion.pl was then run to update fusion.md. Finally, the code for +the "prefixed" attribute is modified so that it considers load + compare +immediate patterns to be like the normal load insns in checking whether +operand[1] is a prefixed instruction. + +I posted a version of patch on March 21st. This patch makes some code changes +suggested in the genfusion.pl code. + +2023-03-21 Michael Meissner + +gcc/ + + PR target/105325 + * gcc/config/rs6000/genfusion.pl (gen_ld_cmpi_p10): Improve generation + of the ld and lwa instructions which use the DS encoding instead of D. + Use the YZ constraint for these loads. Handle prefixed loads better. + Set the sign_extend attribute as appropriate. + * gcc/config/rs6000/fusion.md: Regenerate. + * gcc/config/rs6000/rs6000.md (prefixed attribute): Add fused_load_cmpi + instructions to the list of instructions that might have a prefixed load + instruction. + +gcc/testsuite/ + + PR target/105325 + * g++.target/powerpc/pr105325.C: New test. + * gcc.target/powerpc/fusion-p10-ldcmpi.c: Adjust insn counts. + ==================== Branch work116-dmf, baseline ==================== 2023-03-24 Michael Meissner