From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 60DAD3857B8E; Sun, 2 Apr 2023 08:32:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 60DAD3857B8E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680424351; bh=0VpBsHRjizESUL3FlBCXYvDg5cyr8MDTx/ADV7KfCms=; h=From:To:Subject:Date:From; b=Fr1vT7mTHs2Bh2EUYce7zRzdYlQk6NsfD/KBCIFRb3ww3NsitZ8ZBeqbf4ipsd6Yf zkMRoNG1xlHgpPnPKtpOuJiDuG7e5N9w35H/olS6Yy3JTgyzI+O9YdRc2KVp34o8jZ ALXy5MEgg20Mwa+c9VxRAo7/EDVpEqRypfHL9R7g= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-6973] RISC-V: Fix ICE and codegen error of scalar move in RV32 system. X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 236cde7202aba9c8fee00035f6685fab1eecd808 X-Git-Newrev: db4f7a9b47d148b5074ac15910124c746fb7a96f Message-Id: <20230402083231.60DAD3857B8E@sourceware.org> Date: Sun, 2 Apr 2023 08:32:31 +0000 (GMT) List-Id: https://gcc.gnu.org/g:db4f7a9b47d148b5074ac15910124c746fb7a96f commit r13-6973-gdb4f7a9b47d148b5074ac15910124c746fb7a96f Author: Juzhe-Zhong Date: Wed Mar 29 10:42:59 2023 +0800 RISC-V: Fix ICE and codegen error of scalar move in RV32 system. We need to reset the AVL to 0 or 1 for scalar move for RV32 system, For any non-zero AVL input, we set that to 1, and zero will keep as zero. We are using wrong way (by andi with 1) before to achieve that, and it will cause ICE with const_int, and also wrong behavior, so now we have two code path, one for const_int and one for non-const_int. bug.C:144:2: error: unrecognizable insn: 144 | } | ^ (insn 684 683 685 26 (set (reg:SI 513) (and:SI (const_int 4 [0x4]) (const_int 1 [0x1]))) "bug.C":115:47 -1 (nil)) andi a4,a4,1 ===> sgtu a4,a4,zero vsetlvi tu vsetvli tu vlse vlse gcc/ChangeLog: * config/riscv/riscv-protos.h (gen_avl_for_scalar_move): New function. * config/riscv/riscv-v.cc (gen_avl_for_scalar_move): New function. * config/riscv/vector.md: Fix scalar move bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/scalar_move-6.c: Adapt test. * gcc.target/riscv/rvv/base/scalar_move-9.c: New test. Diff: --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 23 +++++++++++++++++++ gcc/config/riscv/vector.md | 8 ++----- .../gcc.target/riscv/rvv/base/scalar_move-6.c | 8 ------- .../gcc.target/riscv/rvv/base/scalar_move-9.c | 26 ++++++++++++++++++++++ 5 files changed, 52 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index e41f65a0894..4611447ddde 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -205,6 +205,7 @@ enum vlen_enum }; bool slide1_sew64_helper (int, machine_mode, machine_mode, machine_mode, rtx *); +rtx gen_avl_for_scalar_move (rtx); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d7b77fd6123..2e91d019f6c 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -701,4 +701,27 @@ slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode, return true; } +rtx +gen_avl_for_scalar_move (rtx avl) +{ + /* AVL for scalar move has different behavior between 0 and large than 0. */ + if (CONST_INT_P (avl)) + { + /* So we could just set AVL to 1 for any constant other than 0. */ + if (rtx_equal_p (avl, const0_rtx)) + return const0_rtx; + else + return const1_rtx; + } + else + { + /* For non-constant value, we set any non zero value to 1 by + `sgtu new_avl,input_avl,zero` + `vsetvli`. */ + rtx tmp = gen_reg_rtx (Pmode); + emit_insn ( + gen_rtx_SET (tmp, gen_rtx_fmt_ee (GTU, Pmode, avl, const0_rtx))); + return tmp; + } +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1ddc1d3fd39..89927c33a01 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1229,9 +1229,7 @@ else if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (Pmode)) { // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system. - rtx tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (Pmode, operands[4], const1_rtx))); - operands[4] = tmp; + operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]); operands[1] = CONSTM1_RTX (mode); } else @@ -1292,9 +1290,7 @@ vlse64.v */ if (satisfies_constraint_Wb1 (operands[1])) { - rtx tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (Pmode, operands[4], const1_rtx))); - operands[4] = tmp; + operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]); operands[1] = CONSTM1_RTX (mode); } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c index 268ddd7c116..f27f85cdb58 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c @@ -37,8 +37,6 @@ void foo2 (void *base, void *out, size_t vl) /* ** foo3: ** ... -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 -** ... ** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... ** ret @@ -54,8 +52,6 @@ void foo3 (void *base, void *out, size_t vl) /* ** foo4: ** ... -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 -** ... ** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... ** ret @@ -137,8 +133,6 @@ void foo9 (void *base, void *out, size_t vl) /* ** foo10: ** ... -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 -** ... ** vmv.v.i\tv[0-9]+,\s*-15 ** ... */ @@ -167,8 +161,6 @@ void foo11 (void *base, void *out, size_t vl) /* ** foo12: ** ... -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 -** ... ** vmv.v.i\tv[0-9]+,\s*0 ** ... ** ret diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c new file mode 100644 index 00000000000..80ee1b5f0c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */ + +#include "riscv_vector.h" + +vuint64m2_t f1(vuint64m2_t var_17, uint64_t var_60) +{ + vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 0); + return var_16; +} + +vuint64m2_t f2(vuint64m2_t var_17, uint64_t var_60) +{ + vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 4); + return var_16; +} + +vuint64m2_t f3(vuint64m2_t var_17, uint64_t var_60, size_t vl) +{ + vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, vl); + return var_16; +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*0,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {sgtu} 1 } } */