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* [gcc r13-6980] Document signbitm2.
@ 2023-04-03  1:17 hongtao Liu
  0 siblings, 0 replies; only message in thread
From: hongtao Liu @ 2023-04-03  1:17 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:b551ea379947c640358c9f20f71c5c6237d85d0f

commit r13-6980-gb551ea379947c640358c9f20f71c5c6237d85d0f
Author: liuhongt <hongtao.liu@intel.com>
Date:   Fri Mar 31 14:52:51 2023 +0800

    Document signbitm2.
    
    gcc/ChangeLog:
    
            * doc/md.texi: Document signbitm2.

Diff:
---
 gcc/doc/md.texi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 8e3113599fd..edfa51e867a 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -6030,6 +6030,17 @@ floating-point mode.
 
 This pattern is not allowed to @code{FAIL}.
 
+@cindex @code{signbit@var{m}2} instruction pattern
+@item @samp{signbit@var{m}2}
+Store the sign bit of floating-point operand 1 in operand 0.
+@var{m} is either a scalar or vector mode.  When it is a scalar,
+operand 1 has mode @var{m} but operand 0 must have mode @code{SImode}.
+When @var{m} is a vector, operand 1 has the mode @var{m}.
+operand 0's mode should be an vector integer mode which has
+the same number of elements and the same size as mode @var{m}.
+
+This pattern is not allowed to @code{FAIL}.
+
 @cindex @code{significand@var{m}2} instruction pattern
 @item @samp{significand@var{m}2}
 Store the significand of floating-point operand 1 in operand 0.

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