From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 2BBAF3858C50; Mon, 17 Apr 2023 22:28:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2BBAF3858C50 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681770537; bh=Aa1p8JS4oz6lPPa7urw6I6MZFp2P16FSmZlpFol0rvI=; h=From:To:Subject:Date:From; b=QER0ws0jjF/c+BBat+NfvoPfBMgCUu2hhiuBJzwMxf15anGqngNqlKXPcJ1GQ+5nv 0iTxJx3cIHc77SdANomfTvkshOfdBm+U5ET03ARq57ZhhEpnEAiMeuqldXlStAXf04 SoAfjubnevXRcOBn5LWLdKIsIH1fReEOsYHUMDVM= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 577ade1c244e73596489a6e7ba9a0f13f7dd16b6 X-Git-Newrev: 42e15b30179325a78a4786e5a22046e7c2b9a547 Message-Id: <20230417222857.2BBAF3858C50@sourceware.org> Date: Mon, 17 Apr 2023 22:28:57 +0000 (GMT) List-Id: https://gcc.gnu.org/g:42e15b30179325a78a4786e5a22046e7c2b9a547 commit 42e15b30179325a78a4786e5a22046e7c2b9a547 Author: Michael Meissner Date: Mon Apr 17 18:28:54 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 54 +++------------------- .../gcc.target/powerpc/vec-extract-mem-int-1.c | 43 ----------------- .../gcc.target/powerpc/vec-extract-mem-int-2.c | 37 --------------- 3 files changed, 7 insertions(+), 127 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 1c926158eb4..417aff5e24b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3930,52 +3930,13 @@ } [(set_attr "type" "mfvsr")]) -;; Extract a V4SI element from memory with constant element number. -(define_insn_and_split "*vsx_extract_v4si_load" - [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa") - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) (match_dup 4))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SImode); -} - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "4,8,4,8")]) - -;; Extract a V4SI element from memory with constant element number and convert -;; it to DImode with zero or sign extension. -(define_insn_and_split "*vsx_extract_v4si_load_to_di" - [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa") - (any_extend:DI - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "YZ,m,Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (any_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SImode); -} - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "4,8,4,8")]) - -;; Extract a V8HI/V16QI element from memory with constant element number. +;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r,r,v,v") + [(set (match_operand: 0 "register_operand" "=r") (vec_select: - (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q") - (parallel [(match_operand:QI 2 "" "0,n,0,n")]))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") + (parallel [(match_operand:QI 2 "" "n")]))) + (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -3984,9 +3945,8 @@ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "4,8,4,8") - (set_attr "isa" "*,*,p9v,p9v")]) + [(set_attr "type" "load") + (set_attr "length" "8")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c deleted file mode 100644 index db7ea3300e7..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c +++ /dev/null @@ -1,43 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ -/* { dg-require-effective-target p8vector_hw } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode directly into vector registers. */ - -#include - -void -extract_sign_v4si_0 (vector int *p, int *q) -{ - int x = vec_extract (*p, 0); - __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ - *q = x; -} - -void -extract_sign_v4si_1 (vector int *p, int *q) -{ - int x = vec_extract (*p, 1); - __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ - *q = x; -} - -void -extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q) -{ - int x = vec_extract (*p, 0); - __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ - *q = x; -} - -void -extract_v4si_1 (vector unsigned int *p, unsigned int *q) -{ - int x = vec_extract (*p, 1); - __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlfiw[az]x\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]x\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c deleted file mode 100644 index e5452818b0f..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c +++ /dev/null @@ -1,37 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ -/* { dg-require-effective-target p8vector_hw } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold the sign/extension into the load. */ - -#include - -long long -extract_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -unsigned long long -extract_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lwz, no rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ -/* { dg-final { scan-assembler-not {\mrldicl\M} } } */