From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id A7C2C3858D28; Tue, 18 Apr 2023 05:37:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A7C2C3858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681796243; bh=6SIdM6dZcIHa5/rgGgKISzucbSLSSt1d7dmIbjpu5fk=; h=From:To:Subject:Date:From; b=SDf9zDwvknchdLPHQq1NK2SE2diIrozqe+2jiOgvBlD0jr5csFn9GF9KCbsuNE+a5 J3iXf4lrFn/fOfYUWQpDlvlf2vrDPJIp3Mx7iEXg8ehLDx+r1/gA7uQBnpyCEOy1rW Ysy9a52ehUK3oaiZO8n66zWP5iCUNMjoHvia36X4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: ba72e1fd0db48fc19af27061dd52b9ab550a4347 X-Git-Newrev: 7af88e27233ed36c98bf6f0e706e7769195646b6 Message-Id: <20230418053723.A7C2C3858D28@sourceware.org> Date: Tue, 18 Apr 2023 05:37:23 +0000 (GMT) List-Id: https://gcc.gnu.org/g:7af88e27233ed36c98bf6f0e706e7769195646b6 commit 7af88e27233ed36c98bf6f0e706e7769195646b6 Author: Michael Meissner Date: Tue Apr 18 01:37:20 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 94 ++-------------------- .../gcc.target/powerpc/vec-extract-mem-int-1.c | 44 ---------- .../gcc.target/powerpc/vec-extract-mem-int-2.c | 37 --------- .../gcc.target/powerpc/vec-extract-mem-int-3.c | 40 --------- 4 files changed, 7 insertions(+), 208 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 49da544bf28..417aff5e24b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -241,17 +241,6 @@ (TF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (TFmode)")]) -;; Constraint to use for floating point types that a direct conversion -;; from 64-bit integer to floating point. -(define_mode_attr FL_CONSTRAINT [(SF "wa") - (DF "wa") - (KF "v") - (TF "v")]) - -;; Whether to use SIGN or ZERO when depending on the floating point conversion. -(define_code_attr SIGN_ZERO [(float "SIGN") - (unsigned_float "ZERO")]) - ;; Iterator for the 2 short vector types to do a splat from an integer (define_mode_iterator VSX_SPLAT_I [V16QI V8HI]) @@ -3941,81 +3930,13 @@ } [(set_attr "type" "mfvsr")]) -;; Extract a V4SI element from memory with constant element number. -(define_insn_and_split "*vsx_extract_v4si_load" - [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa") - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) (match_dup 4))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SImode); -} - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "4,8,4,8")]) - -;; Extract a V4SI element from memory with constant element number and convert -;; it to DImode with zero or sign extension. -(define_insn_and_split "*vsx_extract_v4si_load_to_di" - [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa") - (any_extend:DI - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "YZ,m,Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (any_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SImode); -} - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "4,8,4,8")]) - -;; Extract a V4SI element from memory with constant element number and convert -;; it to SFmode, DFmode, KFmode, or possibly TFmode using either signed or -;; unsigned conversion. -(define_insn_and_split "*vsx_extract_v4si_load_to_" - [(set (match_operand:FL_CONV 0 "register_operand" "=") - (any_float:FL_CONV - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "m") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")])))) - (clobber (match_scratch:DI 3 "=&b")) - (clobber (match_scratch:DI 4 "="))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 4) - (match_dup 5)) - (set (match_dup 0) - (any_float:FL_CONV (match_dup 4)))] -{ - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2], - operands[3], SImode); - operands[5] = gen_rtx__EXTEND (DImode, new_mem); -} - [(set_attr "type" "fpload") - (set_attr "length" "12")]) - -;; Extract a V8HI/V16QI element from memory with constant element number. +;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r,r,v,v") + [(set (match_operand: 0 "register_operand" "=r") (vec_select: - (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q") - (parallel [(match_operand:QI 2 "" "0,n,0,n")]))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") + (parallel [(match_operand:QI 2 "" "n")]))) + (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -4024,9 +3945,8 @@ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "4,8,4,8") - (set_attr "isa" "*,*,p9v,p9v")]) + [(set_attr "type" "load") + (set_attr "length" "8")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c deleted file mode 100644 index 0be1d471ac5..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c +++ /dev/null @@ -1,44 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ -/* { dg-require-effective-target p8vector_hw } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode directly into vector registers. */ - -#include - -void -extract_sign_v4si_0 (vector int *p, int *q) -{ - int x = vec_extract (*p, 0); - __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ - *q = x; -} - -void -extract_sign_v4si_1 (vector int *p, int *q) -{ - int x = vec_extract (*p, 1); - __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ - *q = x; -} - -void -extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q) -{ - int x = vec_extract (*p, 0); - __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ - *q = x; -} - -void -extract_v4si_1 (vector unsigned int *p, unsigned int *q) -{ - int x = vec_extract (*p, 1); - __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\ml(f|xs)iw[az]x\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]x\M} } } */ -/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c deleted file mode 100644 index bf135789bf8..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c +++ /dev/null @@ -1,37 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ -/* { dg-require-effective-target p8vector_hw } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold the sign/extension into the load. */ - -#include - -long long -extract_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -unsigned long long -extract_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 1); /* lwz, no rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ -/* { dg-final { scan-assembler-not {\mrldicl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c deleted file mode 100644 index 5dfd94832a4..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c +++ /dev/null @@ -1,40 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-require-effective-target float128 } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and convert the value to float, double, and _Float128 by loading the - value directly into a vector register, and not loading up the GPRs - first. */ - -#include - -float -extract_float_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lfiwax or lxsiwax. */ -} - -double -extract_double_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lfiwax or lxsiwax. */ -} - -double -extract_double_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */ -} - -_Float128 -extract_ieee_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 1); /* lfiwzx or lxsiwzx. */ -} - -/* { dg-final { scan-assembler-times {\ml(f|xs)iwax\M} 2 } } */ -/* { dg-final { scan-assembler-times {\ml(f|xs)iwzx\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */ -/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */