From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id DB4C13858D28; Tue, 18 Apr 2023 05:40:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DB4C13858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681796403; bh=htpq57cq7RMp7afrzwofzPH43aKq8gfs4ZIe1xHN2dA=; h=From:To:Subject:Date:From; b=kUGjzygHmV+hC3YuSnrUKaeJGE941sjyt3NQX/Co4NPtq4V8zSWERV4pga8Vu5B3V gMtGP0tFDObfy1tl50H2ZRBONqRmuHfLks6zR8/bxxNxm3tKrESu8CuoAYlx9Db7gF 5lmsyrOIkDvyre2XJKuIlOPLqaOp4F8niJWLQfXo= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Enhance vec_extract from int memory with constant element numbers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 7af88e27233ed36c98bf6f0e706e7769195646b6 X-Git-Newrev: 99bd3be639dee32eaed78afc4dbb069263d20ea4 Message-Id: <20230418054003.DB4C13858D28@sourceware.org> Date: Tue, 18 Apr 2023 05:40:03 +0000 (GMT) List-Id: https://gcc.gnu.org/g:99bd3be639dee32eaed78afc4dbb069263d20ea4 commit 99bd3be639dee32eaed78afc4dbb069263d20ea4 Author: Michael Meissner Date: Tue Apr 18 01:39:39 2023 -0400 Enhance vec_extract from int memory with constant element numbers. This patch adds a combine insn that merges loading up a vec_extract of V4SFmode where the element number is constant combined with a conversion to DFmode. Without this patch, the compiler would load the value into a GPR register and then do a direct move if it needs the value in a vector register. 2023-04-18 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn. gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-int-1.c: New test. Diff: --- gcc/config/rs6000/vsx.md | 33 ++++++++++++---- .../gcc.target/powerpc/vec-extract-mem-int-1.c | 44 ++++++++++++++++++++++ 2 files changed, 70 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 417aff5e24b..26caf81b01b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3930,13 +3930,31 @@ } [(set_attr "type" "mfvsr")]) -;; Optimize extracting a single scalar element from memory. +;; Extract a V4SI element from memory with constant element number. +(define_insn_and_split "*vsx_extract_v4si_load" + [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa") + (vec_select:SI + (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))) + (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 4))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], SImode); +} + [(set_attr "type" "load,load,fpload,fpload") + (set_attr "length" "4,8,4,8")]) + +;; Extract a V8HI/V16QI element from memory with constant element number. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r") + [(set (match_operand: 0 "register_operand" "=r,r,v,v") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") - (parallel [(match_operand:QI 2 "" "n")]))) - (clobber (match_scratch:DI 3 "=&b"))] + (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q") + (parallel [(match_operand:QI 2 "" "0,n,0,n")]))) + (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -3945,8 +3963,9 @@ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load") - (set_attr "length" "8")]) + [(set_attr "type" "load,load,fpload,fpload") + (set_attr "length" "4,8,4,8") + (set_attr "isa" "*,*,p9v,p9v")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c new file mode 100644 index 00000000000..209ca926b97 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target p8vector_hw } */ + +/* Test to verify that the vec_extract with constant element numbers can load + SImode directly into vector registers. */ + +#include + +void +extract_sign_v4si_0 (vector int *p, int *q) +{ + int x = vec_extract (*p, 0); + __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ + *q = x; +} + +void +extract_sign_v4si_1 (vector int *p, int *q) +{ + int x = vec_extract (*p, 1); + __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ + *q = x; +} + +void +extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q) +{ + int x = vec_extract (*p, 0); + __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ + *q = x; +} + +void +extract_v4si_1 (vector unsigned int *p, unsigned int *q) +{ + int x = vec_extract (*p, 1); + __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */ + *q = x; +} + +/* { dg-final { scan-assembler-times {\mlfiw[az]x\M|\mlxsiw[az]x\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mlw[az]x\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */