From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 801BC3858D28; Tue, 18 Apr 2023 05:45:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 801BC3858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681796726; bh=7xy7hiIg/ePuiIOAvnSSsxqBb9vQmRfiwCXpiz7sucI=; h=From:To:Subject:Date:From; b=cKiqrCpURifgdhJ5qulg5Tr9t6+TM1A2a9xxllaL5fXj32W038Oa4W9+v61XUhrL7 QGsK8S8aVmGOTCQWgzXaMBkimxm/ttoz3QYOPyiygYZ12kJxJbDnYAwCrgzZIHs7Rs 0YlqcHXDmxVYWjzSOaE7PCLJYIRyaAtm4/nlEP1o= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Update ChangeLog.* X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 880443108f4b425a0477ff53aeaa5a91d9b45be1 X-Git-Newrev: 222af81c70a3c23cd31b453fdf524a52de07a2ff Message-Id: <20230418054526.801BC3858D28@sourceware.org> Date: Tue, 18 Apr 2023 05:45:26 +0000 (GMT) List-Id: https://gcc.gnu.org/g:222af81c70a3c23cd31b453fdf524a52de07a2ff commit 222af81c70a3c23cd31b453fdf524a52de07a2ff Author: Michael Meissner Date: Tue Apr 18 01:45:23 2023 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 49592e20a32..88bdd55c470 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,5 +1,80 @@ ==================== Branch work119, patch #21 ==================== +Add float/double conversions fro V4SI vec_extract + +This patch adds combiner insns to fold in conversion to float, double, or the +IEEE 128-bit types (both signed and unsigned) of V4SI vec_extract with a +constant element. With this patch, GCC will load the SImode value directly into +the vector register with LFIWZX or LFIWAX instead of doing a LWZ and then moving +the value over with a direct move before the floating point conversion. + +2023-04-18 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (SIGN_ZERO): New code attribute. + (FL_CONSTRAINT): New code attribute. + (vsx_extract_v4si_load_to_ + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v4si_load_to_di): New insn. + +gcc/testsuite/ + + * gcc.target/powerpc/vec-extract-mem-int-2.c: New test. + +==================== Branch work119, patch #21 ==================== + +Enhance vec_extract from int memory with constant element numbers. + +This patch adds a combine insn that merges loading up a vec_extract of V4SFmode +where the element number is constant combined with a conversion to DFmode. +Without this patch, the compiler would load the value into a GPR register and +then do a direct move if it needs the value in a vector register. + +2023-04-18 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn. + +gcc/testsuite/ + + * gcc.target/powerpc/vec-extract-mem-int-1.c: New test. + +==================== Branch work119, patch #22 ==================== + +Fix typo in insn name. + +In doing other work, I noticed that there was an insn: + + vsx_extract_v4sf__load + +Which did not have an iterator. I removed the useless . + +2023-04-17 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v4sf_load): Rename from + vsx_extract_v4sf__load. + +==================== Branch work119, patch #21 ==================== + Improve 64->128 bit zero extension on PowerPC 2023-04-17 Michael Meissner