From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 3E8AD3857340; Wed, 19 Apr 2023 19:14:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3E8AD3857340 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681931653; bh=owIks6dEZ99+AXjOMs3UDxqWiaTHuuIgFggBJVlSjeY=; h=From:To:Subject:Date:From; b=ynvYQ0mAL4roSUhqMImxBz1R5zKPPatKhV88fvDF452HW7zd8i0dgrx6uAdEPvswe Vm1XNDnFjD8M9yFQoD+hqL59OrARMLP5U5kugPvjkYhalpiLXS2H3Ryq3393bVkckE uv9gKlk2zgqt6M8lURxPIUF28L4Ksc3gYqwx3vCw= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 5d283240e71a33664d2ebc4c03009d1676ef7c2e X-Git-Newrev: 5e229034bf8bb04c66b694f108a8eeaa05a72160 Message-Id: <20230419191413.3E8AD3857340@sourceware.org> Date: Wed, 19 Apr 2023 19:14:13 +0000 (GMT) List-Id: https://gcc.gnu.org/g:5e229034bf8bb04c66b694f108a8eeaa05a72160 commit 5e229034bf8bb04c66b694f108a8eeaa05a72160 Author: Michael Meissner Date: Wed Apr 19 15:14:09 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 28 +++++++++------------------- 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 533216321c4..0e681844243 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,12 +223,6 @@ (V8HI "v") (V4SI "wa")]) -;; Mode attribute to give the isa constraint for accessing Altivec registers -;; with vector extract and insert operations. -(define_mode_attr VSX_EX_ISA [(V16QI "p9v") - (V8HI "p8v") - (V4SI "p7v")]) - ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -3957,27 +3951,23 @@ } [(set_attr "type" "mfvsr")]) -;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number. -;; If the element number is 0, we don't need to do a load immediate operation. -;; Likewise for GPRs with offsettable loads, we can fold the offset into the -;; address. For vector registers, we are limited to X-FORM memory addresses. +;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r,r,r,,") + [(set (match_operand: 0 "register_operand" "=r") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q") - (parallel [(match_operand:QI 2 "" "0,n,n,0,n")]))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (mode)" + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") + (parallel [(match_operand:QI 2 "" "n")]))) + (clobber (match_scratch:DI 3 "=&b"))] + "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "4,4,8,4,8") - (set_attr "isa" "*,*,*,,")]) + [(set_attr "type" "load") + (set_attr "length" "8")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var"